dmaengine: cookie bypass for out of order completion

The cookie tracking in dmaengine expects all submissions completed in
order. Some DMA devices like Intel DSA can complete submissions out of
order, especially if configured with a work queue sharing multiple DMA
engines. Add a status DMA_OUT_OF_ORDER that tx_status can be returned for
those DMA devices. The user should use callbacks to track the completion
rather than the DMA cookie. This would address the issue of dmatest
complaining that descriptors are "busy" when the cookie count goes
backwards due to out of order completion. Add DMA_COMPLETION_NO_ORDER
DMA capability to allow the driver to flag the device's ability to complete
operations out of order.

Reported-by: Swathi Kovvuri <swathi.kovvuri@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Tested-by: Swathi Kovvuri <swathi.kovvuri@intel.com>
Link: https://lore.kernel.org/r/158939557151.20335.12404113976045569870.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst
index 56e5833e8a07bc0ec6d9c34acec077ab1959740e..ce68315482b1f218a0a1cd4013ff2c71e4b41865 100644 (file)
--- a/Documentation/driver-api/dmaengine/provider.rst
+++ b/Documentation/driver-api/dmaengine/provider.rst
@@ -239,6 +239,22 @@ Currently, the types available are:
     want to transfer a portion of uncompressed data directly to the
     display to print it
 
+- DMA_COMPLETION_NO_ORDER
+
+  - The device does not support in order completion.
+
+  - The driver should return DMA_OUT_OF_ORDER for device_tx_status if
+    the device is setting this capability.
+
+  - All cookie tracking and checking API should be treated as invalid if
+    the device exports this capability.
+
+  - At this point, this is incompatible with polling option for dmatest.
+
+  - If this cap is set, the user is recommended to provide an unique
+    identifier for each descriptor sent to the DMA device in order to
+    properly track the completion.
+
 These various types will also affect how the source and destination
 addresses change over time.
 
@@ -399,6 +415,9 @@ supported.
   - In the case of a cyclic transfer, it should only take into
     account the current period.
 
+  - Should return DMA_OUT_OF_ORDER if the device does not support in order
+    completion and is completing the operation out of order.
+
   - This function can be called in an interrupt context.
 
 - device_config

diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index b175229a4b01d7992c2356d5134a754dd6bf98fe..18f10154ba191ce322d9f8d7ef1e308e8362c1fb 100644 (file)
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -829,7 +829,10 @@ static int dmatest_func(void *data)
                        result("test timed out", total_tests, src->off, dst->off,
                               len, 0);
                        goto error_unmap_continue;
-               } else if (status != DMA_COMPLETE) {
+               } else if (status != DMA_COMPLETE &&
+                          !(dma_has_cap(DMA_COMPLETION_NO_ORDER,
+                                        dev->cap_mask) &&
+                            status == DMA_OUT_OF_ORDER)) {
                        result(status == DMA_ERROR ?
                               "completion error status" :
                               "completion busy status", total_tests, src->off,
@@ -1007,6 +1010,12 @@ static int dmatest_add_channel(struct dmatest_info *info,
        dtc->chan = chan;
        INIT_LIST_HEAD(&dtc->threads);
 
+       if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) &&
+           info->params.polled) {
+               info->params.polled = false;
+               pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n");
+       }
+
        if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
                if (dmatest == 0) {
                        cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);

diff --git a/drivers/dma/idxd/dma.c b/drivers/dma/idxd/dma.c
index c64c1429d160626e25590974d5daaed4a4a9793d..0c892cbd72e019251d6e5de364a44b6f6a4cb7db 100644 (file)
--- a/drivers/dma/idxd/dma.c
+++ b/drivers/dma/idxd/dma.c
@@ -133,7 +133,7 @@ static enum dma_status idxd_dma_tx_status(struct dma_chan *dma_chan,
                                          dma_cookie_t cookie,
                                          struct dma_tx_state *txstate)
 {
-       return dma_cookie_status(dma_chan, cookie, txstate);
+       return DMA_OUT_OF_ORDER;
 }
 
 /*
@@ -174,6 +174,7 @@ int idxd_register_dma_device(struct idxd_device *idxd)
        INIT_LIST_HEAD(&dma->channels);
        dma->dev = &idxd->pdev->dev;
 
+       dma_cap_set(DMA_COMPLETION_NO_ORDER, dma->cap_mask);
        dma->device_release = idxd_dma_release;
 
        if (idxd->hw.opcap.bits[0] & IDXD_OPCAP_MEMMOVE) {

diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index e1c03339918f99b2d48ccf245ec177baec04599d..9f9a13a2c01f8c5279d4b23cbf582fae6b3b1524 100644 (file)
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -39,6 +39,7 @@ enum dma_status {
        DMA_IN_PROGRESS,
        DMA_PAUSED,
        DMA_ERROR,
+       DMA_OUT_OF_ORDER,
 };
 
 /**
@@ -61,6 +62,7 @@ enum dma_transaction_type {
        DMA_SLAVE,
        DMA_CYCLIC,
        DMA_INTERLEAVE,
+       DMA_COMPLETION_NO_ORDER,
 /* last transaction type for creation of the capabilities mask */
        DMA_TX_TYPE_END,
 };