PM / devfreq: rockchip-dfi: add support for RK3588

Add support for the RK3588 to the driver. The RK3588 has four DDR
channels with a register stride of 0x4000 between the channel
registers, also it has a DDRMON_CTRL register per channel.

Link: https://lore.kernel.org/all/20231018061714.3553817-20-s.hauer@pengutronix.de/
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>

diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index f292031e30a6047d4cbc56d3b52c8ad012bb7589..e2a1e4463b6f5d24b6af41de8e9e41bd52d5c124 100644 (file)
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -26,8 +26,9 @@
 #include <soc/rockchip/rockchip_grf.h>
 #include <soc/rockchip/rk3399_grf.h>
 #include <soc/rockchip/rk3568_grf.h>
+#include <soc/rockchip/rk3588_grf.h>
 
-#define DMC_MAX_CHANNELS       2
+#define DMC_MAX_CHANNELS       4
 
 #define HIWORD_UPDATE(val, mask)       ((val) | (mask) << 16)
 
@@ -723,9 +724,42 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
        return 0;
 };
 
+static int rk3588_dfi_init(struct rockchip_dfi *dfi)
+{
+       struct regmap *regmap_pmu = dfi->regmap_pmu;
+       u32 reg2, reg3, reg4;
+
+       regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, &reg2);
+       regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, &reg3);
+       regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, &reg4);
+
+       /* lower 3 bits of the DDR type */
+       dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
+
+       /*
+        * For version three and higher the upper two bits of the DDR type are
+        * in RK3588_PMUGRF_OS_REG3
+        */
+       if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
+               dfi->ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
+
+       dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
+       dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2;
+       dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) == 0 ? 4 : 2;
+       dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) == 0 ? 4 : 2;
+       dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) |
+                           FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2;
+       dfi->max_channels = 4;
+
+       dfi->ddrmon_stride = 0x4000;
+
+       return 0;
+};
+
 static const struct of_device_id rockchip_dfi_id_match[] = {
        { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
        { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
+       { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
        { },
 };
 

diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h
new file mode 100644 (file)
index 0000000..630b35a
--- /dev/null
+++ b/include/soc/rockchip/rk3588_grf.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __SOC_RK3588_GRF_H
+#define __SOC_RK3588_GRF_H
+
+#define RK3588_PMUGRF_OS_REG2          0x208
+#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO            GENMASK(15, 13)
+#define RK3588_PMUGRF_OS_REG2_BW_CH0                   GENMASK(3, 2)
+#define RK3588_PMUGRF_OS_REG2_BW_CH1                    GENMASK(19, 18)
+#define RK3588_PMUGRF_OS_REG2_CH_INFO                   GENMASK(29, 28)
+
+#define RK3588_PMUGRF_OS_REG3          0x20c
+#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3         GENMASK(13, 12)
+#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION           GENMASK(31, 28)
+
+#define RK3588_PMUGRF_OS_REG4           0x210
+#define RK3588_PMUGRF_OS_REG5           0x214
+
+#endif /* __SOC_RK3588_GRF_H */