drm/amdgpu: add psp v13 ring support

Add callback functions for psp_v13 ring

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 6bdea3f35f3dbd60ae449e622066bc41399ff697..4beee092acf1eefd2eb18649290c93830bd32b5f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -189,11 +189,182 @@ static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
        return ret;
 }
 
+static int psp_v13_0_ring_init(struct psp_context *psp,
+                             enum psp_ring_type ring_type)
+{
+       int ret = 0;
+       struct psp_ring *ring;
+       struct amdgpu_device *adev = psp->adev;
+
+       ring = &psp->km_ring;
+
+       ring->ring_type = ring_type;
+
+       /* allocate 4k Page of Local Frame Buffer memory for ring */
+       ring->ring_size = 0x1000;
+       ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
+                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     &adev->firmware.rbuf,
+                                     &ring->ring_mem_mc_addr,
+                                     (void **)&ring->ring_mem);
+       if (ret) {
+               ring->ring_size = 0;
+               return ret;
+       }
+
+       return 0;
+}
+
+static int psp_v13_0_ring_stop(struct psp_context *psp,
+                              enum psp_ring_type ring_type)
+{
+       int ret = 0;
+       struct amdgpu_device *adev = psp->adev;
+
+       if (amdgpu_sriov_vf(adev)) {
+               /* Write the ring destroy command*/
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
+                            GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
+               /* there might be handshake issue with hardware which needs delay */
+               mdelay(20);
+               /* Wait for response flag (bit 31) */
+               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
+                                  0x80000000, 0x80000000, false);
+       } else {
+               /* Write the ring destroy command*/
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
+                            GFX_CTRL_CMD_ID_DESTROY_RINGS);
+               /* there might be handshake issue with hardware which needs delay */
+               mdelay(20);
+               /* Wait for response flag (bit 31) */
+               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
+                                  0x80000000, 0x80000000, false);
+       }
+
+       return ret;
+}
+
+static int psp_v13_0_ring_create(struct psp_context *psp,
+                                enum psp_ring_type ring_type)
+{
+       int ret = 0;
+       unsigned int psp_ring_reg = 0;
+       struct psp_ring *ring = &psp->km_ring;
+       struct amdgpu_device *adev = psp->adev;
+
+       if (amdgpu_sriov_vf(adev)) {
+               ret = psp_v13_0_ring_stop(psp, ring_type);
+               if (ret) {
+                       DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
+                       return ret;
+               }
+
+               /* Write low address of the ring to C2PMSG_102 */
+               psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
+               /* Write high address of the ring to C2PMSG_103 */
+               psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
+
+               /* Write the ring initialization command to C2PMSG_101 */
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
+                            GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
+
+               /* there might be handshake issue with hardware which needs delay */
+               mdelay(20);
+
+               /* Wait for response flag (bit 31) in C2PMSG_101 */
+               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
+                                  0x80000000, 0x8000FFFF, false);
+
+       } else {
+               /* Wait for sOS ready for ring creation */
+               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
+                                  0x80000000, 0x80000000, false);
+               if (ret) {
+                       DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
+                       return ret;
+               }
+
+               /* Write low address of the ring to C2PMSG_69 */
+               psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
+               /* Write high address of the ring to C2PMSG_70 */
+               psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
+               /* Write size of ring to C2PMSG_71 */
+               psp_ring_reg = ring->ring_size;
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
+               /* Write the ring initialization command to C2PMSG_64 */
+               psp_ring_reg = ring_type;
+               psp_ring_reg = psp_ring_reg << 16;
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+               /* there might be handshake issue with hardware which needs delay */
+               mdelay(20);
+
+               /* Wait for response flag (bit 31) in C2PMSG_64 */
+               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
+                                  0x80000000, 0x8000FFFF, false);
+       }
+
+       return ret;
+}
+
+static int psp_v13_0_ring_destroy(struct psp_context *psp,
+                                 enum psp_ring_type ring_type)
+{
+       int ret = 0;
+       struct psp_ring *ring = &psp->km_ring;
+       struct amdgpu_device *adev = psp->adev;
+
+       ret = psp_v13_0_ring_stop(psp, ring_type);
+       if (ret)
+               DRM_ERROR("Fail to stop psp ring\n");
+
+       amdgpu_bo_free_kernel(&adev->firmware.rbuf,
+                             &ring->ring_mem_mc_addr,
+                             (void **)&ring->ring_mem);
+
+       return ret;
+}
+
+static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
+{
+       uint32_t data;
+       struct amdgpu_device *adev = psp->adev;
+
+       if (amdgpu_sriov_vf(adev))
+               data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
+       else
+               data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
+
+       return data;
+}
+
+static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
+{
+       struct amdgpu_device *adev = psp->adev;
+
+       if (amdgpu_sriov_vf(adev)) {
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
+                            GFX_CTRL_CMD_ID_CONSUME_CMD);
+       } else
+               WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
+}
+
 static const struct psp_funcs psp_v13_0_funcs = {
        .init_microcode = psp_v13_0_init_microcode,
        .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
        .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
        .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
+       .ring_init = psp_v13_0_ring_init,
+       .ring_create = psp_v13_0_ring_create,
+       .ring_stop = psp_v13_0_ring_stop,
+       .ring_destroy = psp_v13_0_ring_destroy,
+       .ring_get_wptr = psp_v13_0_ring_get_wptr,
+       .ring_set_wptr = psp_v13_0_ring_set_wptr,
 };
 
 void psp_v13_0_set_psp_funcs(struct psp_context *psp)