arm64: dts: renesas: r9a09g011: Add ethernet nodes

Add Ethernet nodes to SoC dtsi.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220517081645.3764-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 27810f4ad4cb4fc5db979caa3199e989e9b54e0e..d4cc5459fbb76d62149f19e70836fcbe39bf8ba6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -62,6 +62,57 @@
                        clock-names = "clk";
                };
 
+               avb: ethernet@a3300000 {
+                       compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
+                       reg = <0 0xa3300000 0 0x800>;
+                       interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
+                                    <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
+                                    <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */
+                                    <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */
+                                    <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */
+                                    <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */
+                                    <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */
+                                    <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */
+                                    <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */
+                                    <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */
+                                    <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */
+                       interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15",
+                                         "ch16", "ch17", "ch18", "ch19",
+                                         "ch20", "ch21", "dia", "dib",
+                                         "err_a", "err_b", "mgmt_a", "mgmt_b",
+                                         "line3";
+                       clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
+                                <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
+                                <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
+                       clock-names = "axi", "chi", "gptp";
+                       resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disable";
+               };
+
                cpg: clock-controller@a3500000 {
                        compatible = "renesas,r9a09g011-cpg";
                        reg = <0 0xa3500000 0 0x1000>;