clk: rockchip: rk3568: Add PLL rate for 115.2MHz

Add support for a PLL rate of 115.2MHz so that the Powkiddy RK2023 panel
can run at a requested 60hz (59.99, close enough).

I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231018161848.346947-4-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 16dabe2b9c47f483c772ab3b366464ada70df062..43185668daf63131726ea8950be1b52c8b746518 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -78,6 +78,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
        RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
        RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
        RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
+       RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),
        RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
        RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
        RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),