phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register

Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4.
The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl)
should use the 0x1a0 register, as stated in the downstream dtsi tree.

Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index f4ee5884c076dadd000a754f620bac1b345ffb34..581f09c71667b22551a69ec60ba9d1466ec5d246 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -1116,7 +1116,8 @@
 #define QSERDES_V5_COM_CORE_CLK_EN                     0x174
 #define QSERDES_V5_COM_CMN_CONFIG                      0x17c
 #define QSERDES_V5_COM_CMN_MISC1                       0x19c
-#define QSERDES_V5_COM_CMN_MODE                                0x1a4
+#define QSERDES_V5_COM_CMN_MODE                                0x1a0
+#define QSERDES_V5_COM_CMN_MODE_CONTD                  0x1a4
 #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL               0x1a8
 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0      0x1ac
 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0      0x1b0