staging: iio: meter: ade7854: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-4-jic23@kernel.org

diff --git a/drivers/staging/iio/meter/ade7854.h b/drivers/staging/iio/meter/ade7854.h
index a51e6e3183d38958d14b8482abef8dcfa14dfca6..7a49f8f1016fc8ae8cfc430921aff833fa9a4caa 100644 (file)
--- a/drivers/staging/iio/meter/ade7854.h
+++ b/drivers/staging/iio/meter/ade7854.h
@@ -162,7 +162,7 @@ struct ade7854_state {
                         int bits);
        int irq;
        struct mutex buf_lock;
-       u8 tx[ADE7854_MAX_TX] ____cacheline_aligned;
+       u8 tx[ADE7854_MAX_TX] __aligned(IIO_DMA_MINALIGN);
        u8 rx[ADE7854_MAX_RX];
 
 };