drm/i915: Update IP_VER(12, 50)

With no platform using graphics/media IP_VER(12, 50), replace the
checks throughout the code with IP_VER(12, 55) so the code makes sense
by itself with no additional explanation of previous baggage.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Tvrtko Ursulin <tursulin@ursulin.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320060543.4034215-5-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 3ff3d8889c6cc08fdde5203b33827f3fc27bc6a3..edb54903be0a2bc4ee331209b80b43cb1a391d8e 100644 (file)
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -713,7 +713,7 @@ static int igt_ppgtt_huge_fill(void *arg)
 {
        struct drm_i915_private *i915 = arg;
        unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
-       bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+       bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
        struct i915_address_space *vm;
        struct i915_gem_context *ctx;
        unsigned long max_pages;
@@ -857,7 +857,7 @@ out:
 static int igt_ppgtt_64K(void *arg)
 {
        struct drm_i915_private *i915 = arg;
-       bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+       bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
        struct drm_i915_gem_object *obj;
        struct i915_address_space *vm;
        struct i915_gem_context *ctx;

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 10a7847f1b049119fccb3da9508d90ce03f01d1b..bac15196b4d24ee10354bdbb4bcfb6f90535c86c 100644 (file)
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -117,7 +117,7 @@ static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915)
        if (gen < 12)
                return true;
 
-       if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
                return false;
 
        return HAS_DISPLAY(i915);
@@ -166,7 +166,7 @@ static int prepare_blit(const struct tiled_blits *t,
                src_pitch = t->width; /* in dwords */
                if (src->tiling == CLIENT_TILING_Y) {
                        src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
-                       if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
+                       if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))
                                src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
                } else if (src->tiling == CLIENT_TILING_X) {
                        src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
@@ -177,7 +177,7 @@ static int prepare_blit(const struct tiled_blits *t,
                dst_pitch = t->width; /* in dwords */
                if (dst->tiling == CLIENT_TILING_Y) {
                        dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
-                       if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
+                       if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))
                                dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
                } else if (dst->tiling == CLIENT_TILING_X) {
                        dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
@@ -365,7 +365,7 @@ static u64 tiled_offset(const struct intel_gt *gt,
                v += x;
 
                swizzle = gt->ggtt->bit_6_swizzle_x;
-       } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+       } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
                /* Y-major tiling layout is Tile4 for Xe_HP and beyond */
                v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
 

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1bf13e3d307073956379da22d2d8e989b56cff6..24d1c28201fa30cc08ad8ddcb1d5db1348e124ba 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -827,7 +827,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
                cs = gen12_emit_pipe_control(cs, 0,
                                             PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
 
-       if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+       if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
                /* Wa_1409600907 */
                flags |= PIPE_CONTROL_DEPTH_STALL;
 

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1ade568ffbfa43409129228881abe60d965e8d10..68abc8575bb75d9be981780841a37628f56832a6 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -765,14 +765,14 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
         * and bits have disable semantices.
         */
        media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
-       if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+       if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))
                media_fuse = ~media_fuse;
 
        vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
        vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
                      GEN11_GT_VEBOX_DISABLE_SHIFT;
 
-       if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+       if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {
                fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
                gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
        } else {
@@ -1193,7 +1193,6 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)
                if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
                    GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
                    GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
-                   GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
                    GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
                        regs = xehp_regs;
                        num = ARRAY_SIZE(xehp_regs);

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 42aade0faf2d14d3ff87178c821e0fe24ef23bb1..4bc6c437e7f733bc3267006f85f705e37794ad19 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -493,7 +493,7 @@ __execlists_schedule_in(struct i915_request *rq)
                /* Use a fixed tag for OA and friends */
                GEM_BUG_ON(ce->tag <= BITS_PER_LONG);
                ce->lrc.ccid = ce->tag;
-       } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+       } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
                /* We don't need a strict matching tag, just different values */
                unsigned int tag = ffs(READ_ONCE(engine->context_tag));
 
@@ -613,7 +613,7 @@ static void __execlists_schedule_out(struct i915_request * const rq,
                intel_engine_add_retire(engine, ce->timeline);
 
        ccid = ce->lrc.ccid;
-       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
                ccid >>= XEHP_SW_CTX_ID_SHIFT - 32;
                ccid &= XEHP_MAX_CONTEXT_HW_ID;
        } else {
@@ -1907,7 +1907,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
                ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
                             head, upper_32_bits(csb), lower_32_bits(csb));
 
-               if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+               if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
                        promote = xehp_csb_parse(csb);
                else if (GRAPHICS_VER(engine->i915) >= 12)
                        promote = gen12_csb_parse(csb);
@@ -3479,7 +3479,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
                }
        }
 
-       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
                if (intel_engine_has_preemption(engine))
                        engine->emit_bb_start = xehp_emit_bb_start;
                else
@@ -3582,7 +3582,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
 
        engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
        if (GRAPHICS_VER(engine->i915) >= 11 &&
-           GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 50)) {
+           GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 55)) {
                execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
                execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
        }

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index a425db5ed3a22c38af996ce2183d6fa030ed60b2..2c6d31b8fc1aa31352f8be24398aa343be698d3a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -278,7 +278,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
                intel_uncore_posting_read(uncore,
                                          XELPMP_RING_FAULT_REG);
 
-       } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+       } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
                intel_gt_mcr_multicast_rmw(gt, XEHP_RING_FAULT_REG,
                                           RING_FAULT_VALID, 0);
                intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
@@ -403,7 +403,7 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
        struct drm_i915_private *i915 = gt->i915;
 
        /* From GEN8 onwards we only have one 'All Engine Fault Register' */
-       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                xehp_check_faults(gt);
        else if (GRAPHICS_VER(i915) >= 8)
                gen8_check_faults(gt);

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 5a2bd8de155a8893d853095166d5868f30c6c1e5..29443bf7c06c974090530a692804a3ff691fe76b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -184,7 +184,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
                 * steering.
                 */
        } else if (GRAPHICS_VER(i915) >= 11 &&
-                  GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
+                  GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) {
                gt->steering_table[L3BANK] = icl_l3bank_steering_table;
                gt->info.l3bank_mask =
                        ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
@@ -829,7 +829,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
        if (IS_PONTEVECCHIO(gt->i915)) {
                *group = dss / GEN_DSS_PER_CSLICE;
                *instance = dss % GEN_DSS_PER_CSLICE;
-       } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+       } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
                *group = dss / GEN_DSS_PER_GSLICE;
                *instance = dss % GEN_DSS_PER_GSLICE;
        } else {

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
index 01ac565a56a4ad064865006a71cfe35b0382158f..a67a4c35a4faf8de25d227a2d961f60090e9320a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -54,7 +54,7 @@ int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
  * the topology, so we lookup the DSS ID directly in "slice 0."
  */
 #define _HAS_SS(ss_, gt_, group_, instance_) ( \
-       GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \
+       GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 55) ? \
                intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
                intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
 

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 7811a8c9da0672e4853b3ddfa44123cb5727f4fd..30b128b1fde7c5f3f9c1d09d46dafbe077e8704e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -680,7 +680,7 @@ void setup_private_pat(struct intel_gt *gt)
 
        if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
                xelpg_setup_private_ppat(gt);
-       else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+       else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                xehp_setup_private_ppat(gt);
        else if (GRAPHICS_VER(i915) >= 12)
                tgl_setup_private_ppat(uncore);

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7f1b00cb9924c4e9838948b201596706c8e894c9..b387146ede986f4014fb35c465aaf114835a1014 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -676,7 +676,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 
 static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
 {
-       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
                return 0x70;
        else if (GRAPHICS_VER(engine->i915) >= 12)
                return 0x60;
@@ -690,7 +690,7 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
 
 static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
 {
-       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
                return 0x80;
        else if (GRAPHICS_VER(engine->i915) >= 12)
                return 0x70;
@@ -705,7 +705,7 @@ static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
 
 static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
 {
-       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
                return 0x84;
        else if (GRAPHICS_VER(engine->i915) >= 12)
                return 0x74;
@@ -752,7 +752,7 @@ static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
 static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
 {
 
-       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
                /*
                 * Note that the CSFE context has a dummy slot for CMD_BUF_CCTL
                 * simply to match the RCS context image layout.

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 86ba2f2e485c5f77ad6374c48f8ea44e725097cf..6f7af40771353de0812e8dedc8fc9afddea74682 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -925,7 +925,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
 
        GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
 
-       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                ring_sz = XY_FAST_COLOR_BLT_DW;
        else if (ver >= 8)
                ring_sz = 8;
@@ -936,7 +936,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
        if (IS_ERR(cs))
                return PTR_ERR(cs);
 
-       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
                *cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
                        (XY_FAST_COLOR_BLT_DW - 2);
                *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c931c56945bde33d3e31cc9886e96a3e7accaab7..9fac5e2318e2ba9ff323ee1a942762096e8eda40 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -639,7 +639,7 @@ static void init_l3cc_table(struct intel_gt *gt,
 
        intel_gt_mcr_lock(gt, &flags);
        for_each_l3cc(l3cc, table, i)
-               if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
+               if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55))
                        intel_gt_mcr_multicast_write_fw(gt, XEHP_LNCFCMOCS(i), l3cc);
                else
                        intel_uncore_write_fw(gt->uncore, GEN9_LNCFCMOCS(i), l3cc);

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6a3246240e81de8ed461400f4daf18421675b16f..5eec9cd6199f4512e6e0898ca3d31e5f0918d89f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -642,7 +642,7 @@ void intel_sseu_info_init(struct intel_gt *gt)
 {
        struct drm_i915_private *i915 = gt->i915;
 
-       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                xehp_sseu_info_init(gt);
        else if (GRAPHICS_VER(i915) >= 12)
                gen12_sseu_info_init(gt);
@@ -851,7 +851,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
 {
        if (sseu->max_slices == 0)
                drm_printf(p, "Unavailable\n");
-       else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+       else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                sseu_print_xehp_topology(sseu, p);
        else
                sseu_print_hsw_topology(sseu, p);

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9484b38acc72ca5d5dd5490d2dcc973900670e3d..b686f68d3a5a21a6ebf9a426f2ae29eea50603c3 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2770,7 +2770,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
                wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
                                        THREAD_EX_ARB_MODE_RR_AFTER_DEP);
 
-       if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+       if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
                wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
 }
 
@@ -2973,7 +2973,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
        const struct i915_range *mcr_ranges;
        int i;
 
-       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                mcr_ranges = mcr_ranges_xehp;
        else if (GRAPHICS_VER(i915) >= 12)
                mcr_ranges = mcr_ranges_gen12;

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2b450c43bbd7f1562986d41d1853dda0f4a95bd7..2fa7a7505aaf213a35eff907933a533de947d6a9 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -286,7 +286,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 
        /* Wa_22012773006:gen11,gen12 < XeHP */
        if (GRAPHICS_VER(gt->i915) >= 11 &&
-           GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
+           GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 55))
                flags |= GUC_WA_POLLCS;
 
        /* Wa_14014475959 */

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index f7372f736a776028f84e552a2e5aba86829c543d..3345aed2f88a9ad883c25cbda097f2f5bc481fcb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -393,7 +393,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
 
        /* add in local MOCS registers */
        for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
-               if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+               if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
                        ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
                else
                        ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
@@ -503,7 +503,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
 
 #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
 #define XEHP_LR_HW_CONTEXT_SIZE (96 * sizeof(u32))
-#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50) ? \
+#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55) ? \
                                    XEHP_LR_HW_CONTEXT_SIZE : \
                                    LR_HW_CONTEXT_SIZE)
 #define LRC_SKIP_SIZE(i915) (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SZ(i915))

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 52332bb143395e80b362a0ba91386b8eef5f7d41..a35e32695e1ba7125925224cf5eb7a5a8687a51e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -26,7 +26,7 @@ static void guc_prepare_xfer(struct intel_gt *gt)
                         GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
                         GUC_ENABLE_MIA_CLOCK_GATING;
 
-       if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 55))
                shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
                              GUC_ENABLE_MIA_CACHING;
 

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f3dcae4b9d455ed37d3cc3fd1635760cd9e264af..03ce1255bbc2734fdae8ae09429fe23d6bdc6363 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4507,7 +4507,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
         */
 
        engine->emit_bb_start = gen8_emit_bb_start;
-       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
                engine->emit_bb_start = xehp_emit_bb_start;
 }
 

diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 5c3fec63cb4c14960719aa9daf9ada8fbc4e7020..fc4c3d4e2b40e80ff42f7520aa5db8bf5478636f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -160,7 +160,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
                break;
        case I915_PARAM_SLICE_MASK:
                /* Not supported from Xe_HP onward; use topology queries */
-               if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+               if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                        return -EINVAL;
 
                value = sseu->slice_mask;
@@ -169,7 +169,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
                break;
        case I915_PARAM_SUBSLICE_MASK:
                /* Not supported from Xe_HP onward; use topology queries */
-               if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+               if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                        return -EINVAL;
 
                /* Only copy bits from the first slice */

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index a0b784ebaddda4ee00518a40ebcbde24b4285465..2594eb10c5594a6657494697d48d6c5056632ea9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1245,8 +1245,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
                if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)
                        ee->fault_reg = intel_uncore_read(engine->uncore,
                                                          XELPMP_RING_FAULT_REG);
-
-               else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+               else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
                        ee->fault_reg = intel_gt_mcr_read_any(engine->gt,
                                                              XEHP_RING_FAULT_REG);
                else if (GRAPHICS_VER(i915) >= 12)
@@ -1852,7 +1851,7 @@ static void gt_record_global_regs(struct intel_gt_coredump *gt)
        if (GRAPHICS_VER(i915) == 7)
                gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
 
-       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
                gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
                                                        XEHP_FAULT_TLB_DATA0);
                gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9052889dc0dc846181345968dbcfca67cbdbecba..0b1cd4c7a525f4b53049936f7c31c8a0da8d8509 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -292,7 +292,7 @@ static u32 i915_perf_stream_paranoid = true;
 #define OAREPORT_REASON_CTX_SWITCH     (1<<3)
 #define OAREPORT_REASON_CLK_RATIO      (1<<5)
 
-#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
 
 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
  *
@@ -817,7 +817,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
                 */
 
                if (oa_report_ctx_invalid(stream, report) &&
-                   GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 50)) {
+                   GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 55)) {
                        ctx_id = INVALID_CTX_ID;
                        oa_context_id_squash(stream, report32);
                }
@@ -1419,7 +1419,7 @@ static int gen12_get_render_context_id(struct i915_perf_stream *stream)
 
                mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
                        (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
-       } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
+       } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 55)) {
                ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
                        (XEHP_SW_CTX_ID_SHIFT - 32);
 
@@ -4122,7 +4122,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
                        props->hold_preemption = !!value;
                        break;
                case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
-                       if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
+                       if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 55)) {
                                drm_dbg(&perf->i915->drm,
                                        "SSEU config not supported on gfx %x\n",
                                        GRAPHICS_VER_FULL(perf->i915));

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 3baa2f54a86ed8aa246381b858d3a513365c5694..14d9ec0ed777140f1d66f1b910e4a3d56a5407a3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -105,7 +105,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,
        struct intel_engine_cs *engine;
        struct i915_engine_class_instance classinstance;
 
-       if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+       if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
                return -ENODEV;
 
        classinstance = *((struct i915_engine_class_instance *)&query_item->flags);

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index b525318dbd53b5d3af87decda8150f53148eeeb3..4d2b15dbe9acd81a5d33ec76a72e13e6c1a4642a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2714,7 +2714,7 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
                 * the forcewake domain if any of the other engines
                 * in the same media slice are present.
                 */
-               if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) {
+               if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 55) && i % 2 == 0) {
                        if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1)))
                                continue;