arm64: irqflags: Introduce explicit debugging for IRQ priorities

Using IRQ priority masking to enable/disable interrupts is a bit
sensitive as it requires to deal with both ICC_PMR_EL1 and PSR.I.

Introduce some validity checks to both highlight the states in which
functions dealing with IRQ enabling/disabling can (not) be called, and
bark a warning when called in an unexpected state.

Since these checks are done on hotpaths, introduce a build option to
choose whether to do the checking.

Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index acd72e5f78ae3eac1fb1bebcee35bab423107c9d..bd3915ae7b53df766eae028b1ceac88daa38e049 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1436,6 +1436,17 @@ config ARM64_PSEUDO_NMI
 
          If unsure, say N
 
+if ARM64_PSEUDO_NMI
+config ARM64_DEBUG_PRIORITY_MASKING
+       bool "Debug interrupt priority masking"
+       help
+         This adds runtime checks to functions enabling/disabling
+         interrupts when using priority masking. The additional checks verify
+         the validity of ICC_PMR_EL1 when calling concerned functions.
+
+         If unsure, say N
+endif
+
 config RELOCATABLE
        bool
        help

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index bc895c869892ce7ae8f82faae98c17d05c654850..693a086e2148caedd112f3aebe2a73df9286812e 100644 (file)
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -617,6 +617,12 @@ static inline bool system_uses_irq_prio_masking(void)
               cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);
 }
 
+static inline bool system_has_prio_mask_debugging(void)
+{
+       return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
+              system_uses_irq_prio_masking();
+}
+
 #define ARM64_SSBD_UNKNOWN             -1
 #define ARM64_SSBD_FORCE_DISABLE       0
 #define ARM64_SSBD_KERNEL              1

diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h
index f93204f319daaa5481d67c584b5869e02e4139b0..eca5bee1d85b23db1606c4049cbbafeb6300e438 100644 (file)
--- a/arch/arm64/include/asm/daifflags.h
+++ b/arch/arm64/include/asm/daifflags.h
@@ -28,6 +28,10 @@
 /* mask/save/unmask/restore all exceptions, including interrupts. */
 static inline void local_daif_mask(void)
 {
+       WARN_ON(system_has_prio_mask_debugging() &&
+               (read_sysreg_s(SYS_ICC_PMR_EL1) == (GIC_PRIO_IRQOFF |
+                                                   GIC_PRIO_PSR_I_SET)));
+
        asm volatile(
                "msr    daifset, #0xf           // local_daif_mask\n"
                :
@@ -62,6 +66,9 @@ static inline void local_daif_restore(unsigned long flags)
 {
        bool irq_disabled = flags & PSR_I_BIT;
 
+       WARN_ON(system_has_prio_mask_debugging() &&
+               !(read_sysreg(daif) & PSR_I_BIT));
+
        if (!irq_disabled) {
                trace_hardirqs_on();
 

diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h
index a1372722f12ea47550b67f637f65a78a5084930a..cac2d2a3c24e9d098773716ed100b9890f28226d 100644 (file)
--- a/arch/arm64/include/asm/irqflags.h
+++ b/arch/arm64/include/asm/irqflags.h
@@ -40,6 +40,12 @@
  */
 static inline void arch_local_irq_enable(void)
 {
+       if (system_has_prio_mask_debugging()) {
+               u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);
+
+               WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
+       }
+
        asm volatile(ALTERNATIVE(
                "msr    daifclr, #2             // arch_local_irq_enable\n"
                "nop",
@@ -53,6 +59,12 @@ static inline void arch_local_irq_enable(void)
 
 static inline void arch_local_irq_disable(void)
 {
+       if (system_has_prio_mask_debugging()) {
+               u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);
+
+               WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
+       }
+
        asm volatile(ALTERNATIVE(
                "msr    daifset, #2             // arch_local_irq_disable",
                __msr_s(SYS_ICC_PMR_EL1, "%0"),