wifi: mt76: mt7996: set DMA mask to 36 bits for boards with more than 4GB of RAM
authorSujuan Chen <sujuan.chen@mediatek.com>
Fri, 17 Nov 2023 17:13:19 +0000 (18:13 +0100)
committerFelix Fietkau <nbd@nbd.name>
Mon, 11 Dec 2023 12:11:52 +0000 (13:11 +0100)
Introduce the capability to run mt7996 driver on boards with more than
4GB of memory.

Co-developed-by: Rex Lu <rex.lu@mediatek.com>
Signed-off-by: Rex Lu <rex.lu@mediatek.com>
Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
drivers/net/wireless/mediatek/mt76/dma.c
drivers/net/wireless/mediatek/mt76/dma.h
drivers/net/wireless/mediatek/mt76/mmio.c
drivers/net/wireless/mediatek/mt76/mt76.h
drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
drivers/net/wireless/mediatek/mt76/mt7996/dma.c
drivers/net/wireless/mediatek/mt76/mt7996/mac.c
drivers/net/wireless/mediatek/mt76/mt7996/mmio.c
drivers/net/wireless/mediatek/mt76/mt7996/pci.c
drivers/net/wireless/mediatek/mt76/mt7996/regs.h

index 439cdfab6f67fc4a73baef659380a1f01cfca120..8bbb0e17229d715f5415aac0c2b1a9f1e4e340e0 100644 (file)
@@ -232,8 +232,8 @@ mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q,
        struct mt76_queue_entry *entry = &q->entry[q->head];
        struct mt76_txwi_cache *txwi = NULL;
        struct mt76_desc *desc;
-       u32 buf1 = 0, ctrl;
        int idx = q->head;
+       u32 buf1 = 0, ctrl;
        int rx_token;
 
        if (mt76_queue_is_wed_rro_ind(q)) {
@@ -246,6 +246,9 @@ mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q,
 
        desc = &q->desc[q->head];
        ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+       buf1 = FIELD_PREP(MT_DMA_CTL_SDP0_H, buf->addr >> 32);
+#endif
 
        if (mt76_queue_is_wed_rx(q)) {
                txwi = mt76_get_rxwi(dev);
@@ -312,11 +315,18 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
                entry->dma_len[0] = buf[0].len;
 
                ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+               info |= FIELD_PREP(MT_DMA_CTL_SDP0_H, buf[0].addr >> 32);
+#endif
                if (i < nbufs - 1) {
                        entry->dma_addr[1] = buf[1].addr;
                        entry->dma_len[1] = buf[1].len;
                        buf1 = buf[1].addr;
                        ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+                       info |= FIELD_PREP(MT_DMA_CTL_SDP1_H,
+                                          buf[1].addr >> 32);
+#endif
                        if (buf[1].skip_unmap)
                                entry->skip_buf1 = true;
                }
index c60dfb817227b98a6d5658c8adcf9e9798d73c6b..c479cc6388eff4f260cb3e39898ed3e3b0a5c499 100644 (file)
@@ -19,6 +19,8 @@
 #define MT_DMA_CTL_TO_HOST_A           BIT(12)
 #define MT_DMA_CTL_DROP                        BIT(14)
 #define MT_DMA_CTL_TOKEN               GENMASK(31, 16)
+#define MT_DMA_CTL_SDP1_H              GENMASK(19, 16)
+#define MT_DMA_CTL_SDP0_H              GENMASK(3, 0)
 #define MT_DMA_CTL_WO_DROP             BIT(8)
 
 #define MT_DMA_PPE_CPU_REASON          GENMASK(15, 11)
index 4a006409a3732f306a8074ffa9acc589c20dd38b..c3e0e23e0161ac7daac34190c3b363b99fc94399 100644 (file)
@@ -142,8 +142,11 @@ u32 mt76_mmio_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
                        goto unmap;
                }
 
-               desc->token |= cpu_to_le32(FIELD_PREP(MT_DMA_CTL_TOKEN,
-                                                     token));
+               token = FIELD_PREP(MT_DMA_CTL_TOKEN, token);
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+               token |= FIELD_PREP(MT_DMA_CTL_SDP0_H, addr >> 32);
+#endif
+               desc->token |= cpu_to_le32(token);
                desc++;
        }
 
index d66864afaf381dd8804e3f7cfbb55ab2259898dc..b20c34d5a0f7cc4d1b9f83df2a8a0a45a8e416ee 100644 (file)
@@ -183,7 +183,7 @@ struct mt76_queue_entry {
                struct urb *urb;
                int buf_sz;
        };
-       u32 dma_addr[2];
+       dma_addr_t dma_addr[2];
        u16 dma_len[2];
        u16 wcid;
        bool skip_buf0:1;
index ecd7889209f3dc7dda551a814e5f6c35ae180e94..83dcd964bfd0450ee104020129d9cf16837da7d1 100644 (file)
@@ -261,6 +261,9 @@ enum tx_mgnt_type {
 
 #define MT_TXD9_WLAN_IDX               GENMASK(23, 8)
 
+#define MT_TXP_BUF_LEN                 GENMASK(11, 0)
+#define MT_TXP_DMA_ADDR_H              GENMASK(15, 12)
+
 #define MT_TX_RATE_STBC                        BIT(14)
 #define MT_TX_RATE_NSS                 GENMASK(13, 10)
 #define MT_TX_RATE_MODE                        GENMASK(9, 6)
index 0bc4681fc18ab67e7c6fa37a7cb6c8a8ca5d9098..483ad81b6eec6335cfbd33bbfc16deaf058a8b3f 100644 (file)
@@ -230,7 +230,8 @@ void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset)
                if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed))
                        mt76_set(dev, MT_WFDMA0_GLO_CFG,
                                 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
-                                MT_WFDMA0_GLO_CFG_OMIT_TX_INFO);
+                                MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
+                                MT_WFDMA0_GLO_CFG_EXT_EN);
                else
                        mt76_set(dev, MT_WFDMA0_GLO_CFG,
                                 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
@@ -243,7 +244,8 @@ void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset)
                                 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
                                 MT_WFDMA0_GLO_CFG_RX_DMA_EN |
                                 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
-                                MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
+                                MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 |
+                                MT_WFDMA0_GLO_CFG_EXT_EN);
        }
 
        /* enable interrupts for TX/RX rings */
index ccdec1cc9b2c7be457b969adccec3619154230c9..53258488d49f36a0e041840da9b9679f65e836d2 100644 (file)
@@ -942,8 +942,16 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
 
        txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE);
        for (i = 0; i < nbuf; i++) {
+               u16 len;
+
+               len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len);
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+               len |= FIELD_PREP(MT_TXP_DMA_ADDR_H,
+                                 tx_info->buf[i + 1].addr >> 32);
+#endif
+
                txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
-               txp->fw.len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
+               txp->fw.len[i] = cpu_to_le16(len);
        }
        txp->fw.nbuf = nbuf;
 
index b1119f62c946de50e919855adbe30a631641063f..c50d89a445e9560672aeab8752de112220c9ab1c 100644 (file)
@@ -287,7 +287,6 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
        struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
        struct pci_dev *pci_dev = pdev_ptr;
        u32 hif1_ofs = 0;
-       int ret;
 
        if (!wed_enable)
                return 0;
@@ -407,14 +406,6 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
        *irq = wed->irq;
        dev->mt76.dma_dev = wed->dev;
 
-       ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
-       if (ret)
-               return ret;
-
-       ret = dma_set_coherent_mask(wed->dev, DMA_BIT_MASK(32));
-       if (ret)
-               return ret;
-
        return 1;
 #else
        return 0;
index a35939cbf3bfcd006ad66a4f40999529ee73f649..04056181368a69b81df51294ea6987d512e7c6a6 100644 (file)
@@ -111,7 +111,11 @@ static int mt7996_pci_probe(struct pci_dev *pdev,
 
        pci_set_master(pdev);
 
-       ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+       ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
+       if (ret)
+               return ret;
+
+       ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
        if (ret)
                return ret;
 
index 21637e3aae427eabbe6b8b749dc651e05927a1c8..47b429d8bfbe5d9022284346784c1d59aa9d3a83 100644 (file)
@@ -405,9 +405,10 @@ enum offs_rev {
 #define MT_WFDMA0_GLO_CFG                      MT_WFDMA0(0x208)
 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN            BIT(0)
 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN            BIT(2)
-#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO         BIT(28)
-#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO         BIT(27)
 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2   BIT(21)
+#define MT_WFDMA0_GLO_CFG_EXT_EN               BIT(26)
+#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO         BIT(27)
+#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO         BIT(28)
 
 #define MT_WFDMA0_PAUSE_RX_Q_45_TH             MT_WFDMA0(0x268)
 #define MT_WFDMA0_PAUSE_RX_Q_67_TH             MT_WFDMA0(0x26c)