mmc: sdhci-of-dwcmshc: properly determine max clock on Rockchip

Currently .get_max_clock returns the current clock rate for cclk_emmc
on rk35xx, thus max clock gets set to whatever bootloader set it to.

In case of u-boot, it is intentionally reset to 50 MHz if it boots
from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and
HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit
clears appropriate caps if host->mmc->f_max is < 52MHz

cclk_emmc is not a fixed clock on rk35xx, so using
sdhci_pltfm_clk_get_max_clock is not appropriate here.

Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index d1490469184be03c03ffa2c6684d7e1d0c1f635d..e68cd87998c822442871c0b22567aab8efbc00d8 100644 (file)
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
                return pltfm_host->clock;
 }
 
+static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
+{
+       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+       return clk_round_rate(pltfm_host->clk, ULONG_MAX);
+}
+
 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
                                     struct mmc_request *mrq)
 {
@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
        .set_clock              = dwcmshc_rk3568_set_clock,
        .set_bus_width          = sdhci_set_bus_width,
        .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
-       .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
+       .get_max_clock          = rk35xx_get_max_clock,
        .reset                  = rk35xx_sdhci_reset,
        .adma_write_desc        = dwcmshc_adma_write_desc,
 };