clk: qcom: cpu-8996: correct PLL programming

Change PLL programming to follow the downstream setup.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-4-dmitry.baryshkov@linaro.org

diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index ee76ef958d31c6980a9418c5f63ccda49f11151c..ed8cb558e1aab961b5807d821445321d4f8948fc 100644 (file)
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -93,12 +93,9 @@ static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
 static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
        [PLL_OFF_L_VAL] = 0x04,
        [PLL_OFF_ALPHA_VAL] = 0x08,
-       [PLL_OFF_ALPHA_VAL_U] = 0x0c,
        [PLL_OFF_USER_CTL] = 0x10,
-       [PLL_OFF_USER_CTL_U] = 0x14,
        [PLL_OFF_CONFIG_CTL] = 0x18,
        [PLL_OFF_TEST_CTL] = 0x20,
-       [PLL_OFF_TEST_CTL_U] = 0x24,
        [PLL_OFF_STATUS] = 0x28,
 };
 
@@ -106,8 +103,10 @@ static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
 
 static const struct alpha_pll_config hfpll_config = {
        .l = 60,
-       .config_ctl_val = 0x200d4aa8,
+       .config_ctl_val = 0x200d4828,
        .config_ctl_hi_val = 0x006,
+       .test_ctl_val = 0x1c000000,
+       .test_ctl_hi_val = 0x00004000,
        .pre_div_mask = BIT(12),
        .post_div_mask = 0x3 << 8,
        .post_div_val = 0x1 << 8,