return ret;
 }
 
-#define CPU_AFINITY_MASK 0xFFF
-#define PWRCL_CPU_REG_MASK 0x3
-#define PERFCL_CPU_REG_MASK 0x103
+#define CPU_CLUSTER_AFFINITY_MASK 0xf00
+#define PWRCL_AFFINITY_MASK 0x000
+#define PERFCL_AFFINITY_MASK 0x100
 
 #define L2ACDCR_REG 0x580ULL
 #define L2ACDTD_REG 0x581ULL
        if (val == 0x00006a11)
                goto out;
 
-       hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK;
-
        kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006a11);
        kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f);
        kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601);
 
-       if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) {
-               regmap_write(regmap, PWRCL_REG_OFFSET + SSSCTL_OFFSET, 0xf);
-               kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
-       }
+       kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
 
-       if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) {
-               kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
+       hwid = read_cpuid_mpidr();
+       if ((hwid & CPU_CLUSTER_AFFINITY_MASK) == PWRCL_AFFINITY_MASK)
+               regmap_write(regmap, PWRCL_REG_OFFSET + SSSCTL_OFFSET, 0xf);
+       else
                regmap_write(regmap, PERFCL_REG_OFFSET + SSSCTL_OFFSET, 0xf);
-       }
 
 out:
        spin_unlock_irqrestore(&qcom_clk_acd_lock, flags);