platform/x86: intel_pmc_core: Add Intel Tiger Lake support

Add Intel Tiger Lake to the list of the platforms that driver supports
for the PMC device.

Just like Ice Lake, Tiger Lake can also reuse all the Cannon Lake PCH
IPs. Since Tiger Lake has almost the same number of PCH IPs as Ice Lake,
reuse Ice Lake's PPFEAR_NUM_ENTRIES instead of defining a new macro.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: David E. Box <david.e.box@intel.com>
Cc: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Cc: Tony Luck <tony.luck@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index eb22c2f84ceffa6f4c5495989a686a835e50e2f1..a86c2f1ba889b1a16e9746edda5c09c36891eb7e 100644 (file)
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -191,7 +191,10 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
        {"SDX",                 BIT(4)},
        {"SPE",                 BIT(5)},
        {"Fuse",                BIT(6)},
-       /* Reserved for Cannon Lake but valid for Ice Lake and Comet Lake */
+       /*
+        * Reserved for Cannon Lake but valid for Ice Lake, Comet Lake
+        * and Tiger Lake.
+        */
        {"SBR8",                BIT(7)},
 
        {"CSME_FSC",            BIT(0)},
@@ -235,7 +238,10 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
        {"HDA_PGD4",            BIT(2)},
        {"HDA_PGD5",            BIT(3)},
        {"HDA_PGD6",            BIT(4)},
-       /* Reserved for Cannon Lake but valid for Ice Lake and Comet Lake */
+       /*
+        * Reserved for Cannon Lake but valid for Ice Lake, Comet Lake
+        * and Tiger Lake.
+        */
        {"PSF6",                BIT(5)},
        {"PSF7",                BIT(6)},
        {"PSF8",                BIT(7)},
@@ -266,6 +272,24 @@ static const struct pmc_bit_map *ext_icl_pfear_map[] = {
        NULL
 };
 
+static const struct pmc_bit_map tgl_pfear_map[] = {
+       /* Tiger Lake generation onwards only */
+       {"PSF9",                BIT(0)},
+       {"RES_66",              BIT(1)},
+       {"RES_67",              BIT(2)},
+       {"RES_68",              BIT(3)},
+       {"RES_69",              BIT(4)},
+       {"RES_70",              BIT(5)},
+       {"TBTLSX",              BIT(6)},
+       {}
+};
+
+static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
+       cnp_pfear_map,
+       tgl_pfear_map,
+       NULL
+};
+
 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
        {"AUDIO_D3",            BIT(0)},
        {"OTG_D3",              BIT(1)},
@@ -384,6 +408,22 @@ static const struct pmc_reg_map icl_reg_map = {
        .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
 };
 
+static const struct pmc_reg_map tgl_reg_map = {
+       .pfear_sts = ext_tgl_pfear_map,
+       .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
+       .slps0_dbg_maps = cnp_slps0_dbg_maps,
+       .ltr_show_sts = cnp_ltr_show_map,
+       .msr_sts = msr_map,
+       .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
+       .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+       .regmap_length = CNP_PMC_MMIO_REG_LEN,
+       .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+       .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
+       .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+       .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+       .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
+};
+
 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 {
        return readb(pmcdev->regbase + offset);
@@ -839,6 +879,8 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
        INTEL_CPU_FAM6(ICELAKE_NNPI, icl_reg_map),
        INTEL_CPU_FAM6(COMETLAKE, cnp_reg_map),
        INTEL_CPU_FAM6(COMETLAKE_L, cnp_reg_map),
+       INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map),
+       INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map),
        {}
 };
 

diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index 4b9f9ad6b692285ff14545a7086623a12889aca7..99acdc051342c2da2c982f6336ec126cc8f55c1e 100644 (file)
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -186,6 +186,8 @@ enum ppfear_regs {
 #define ICL_NUM_IP_IGN_ALLOWED                 20
 #define ICL_PMC_LTR_WIGIG                      0x1BFC
 
+#define TGL_NUM_IP_IGN_ALLOWED                 22
+
 struct pmc_bit_map {
        const char *name;
        u32 bit_mask;