drm/amd/display: Add BLNDGAM memory shutdown support

[Why]
The BLNDGAM memory blocks should be powered down when they're not in
use. This will reduce power consumption.

[How]
1. Write to BLNDGAM_MEM_PWR_FORCE to put memory to shutdown when BLNDGAM
   is not used.
2. Added a debug option to allow this behaviour to be turned off

Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index 29231528f0525bec87fd1e4f4758eee6e846763e..052bab3e5e8ed3ded283d211da784da62dbef304 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -500,9 +500,14 @@ static void dpp3_power_on_blnd_lut(
 {
        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 
-       REG_SET(CM_MEM_PWR_CTRL, 0,
-                       BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
-
+       if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
+               REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, power_on ? 0 : 3);
+               if (power_on)
+                       REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
+       } else {
+               REG_SET(CM_MEM_PWR_CTRL, 0,
+                               BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
+       }
 }
 
 static void dpp3_configure_blnd_lut(
@@ -675,6 +680,8 @@ bool dpp3_program_blnd_lut(
 
        if (params == NULL) {
                REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
+               if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
+                       dpp3_power_on_blnd_lut(dpp_base, false);
                return false;
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 81bf2ecc283140d6cd09b52090475eac3bf91dde..2ae5e1f93dd40bca4fe7cccec5fc42403366b5cf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -343,6 +343,7 @@
        TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
 
 #define DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)\
+       TF_SF(CM0_CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, mask_sh), \
        TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE, mask_sh), \
        TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, mask_sh), \
        TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, mask_sh), \
@@ -446,7 +447,8 @@
        type CM_BLNDGAM_MODE_CURRENT; \
        type CM_BLNDGAM_SELECT_CURRENT; \
        type CM_BLNDGAM_SELECT; \
-       type GAMCOR_MEM_PWR_STATE
+       type GAMCOR_MEM_PWR_STATE; \
+       type BLNDGAM_MEM_PWR_STATE
 
 struct dcn3_dpp_shift {
        DPP_REG_FIELD_LIST_DCN3(uint8_t);