psr_power_opt_ds_disable_allow = 0x100,
 };
 
+enum dml_hostvm_override_opts {
+       DML_HOSTVM_NO_OVERRIDE = 0x0,
+       DML_HOSTVM_OVERRIDE_FALSE = 0x1,
+       DML_HOSTVM_OVERRIDE_TRUE = 0x2,
+};
+
 enum dcc_option {
        DCC_ENABLE = 0,
        DCC_DISABLE = 1,
        bool extended_blank_optimization;
        union aux_wake_wa_options aux_wake_wa;
        uint8_t psr_power_use_phy_fsm;
+       enum dml_hostvm_override_opts dml_hostvm_override;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;
 
        .enable_sw_cntl_psr = true,
        .apply_vendor_specific_lttpr_wa = true,
        .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
+       .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
                 * intermittently experienced depending on peak b/w requirements.
                 */
                pipes[pipe_cnt].pipe.src.immediate_flip = true;
-
                pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
                pipes[pipe_cnt].pipe.src.gpuvm = true;
                pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
                pipes[pipe_cnt].pipe.src.dcc_rate = 3;
                pipes[pipe_cnt].dout.dsc_input_bpc = 0;
 
+               if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)
+                       pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
+               else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
+                       pipes[pipe_cnt].pipe.src.hostvm = false;
+               else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
+                       pipes[pipe_cnt].pipe.src.hostvm = true;
+
                if (pipes[pipe_cnt].dout.dsc_enable) {
                        switch (timing->display_color_depth) {
                        case COLOR_DEPTH_888: