mci.val = mchk->mcic;
/* take care of lazy register loading */
- fpu_stfpc(&vcpu->run->s.regs.fpc);
- if (cpu_has_vx())
- save_vx_regs((__vector128 *)&vcpu->run->s.regs.vrs);
- else
- save_fp_regs((freg_t *)&vcpu->run->s.regs.fprs);
+ kvm_s390_fpu_store(vcpu->run);
save_access_regs(vcpu->run->s.regs.acrs);
if (MACHINE_HAS_GS && vcpu->arch.gs_enabled)
save_gs_cb(current->thread.gs_cb);
}
save_access_regs(vcpu->arch.host_acrs);
restore_access_regs(vcpu->run->s.regs.acrs);
- fpu_lfpc_safe(&vcpu->run->s.regs.fpc);
- if (cpu_has_vx())
- load_vx_regs((__vector128 *)&vcpu->run->s.regs.vrs);
- else
- load_fp_regs((freg_t *)&vcpu->run->s.regs.fprs);
+ kvm_s390_fpu_load(vcpu->run);
/* Sync fmt2 only data */
if (likely(!kvm_s390_pv_cpu_is_protected(vcpu))) {
sync_regs_fmt2(vcpu);
kvm_run->s.regs.pfc = vcpu->arch.pfault_compare;
save_access_regs(vcpu->run->s.regs.acrs);
restore_access_regs(vcpu->arch.host_acrs);
- fpu_stfpc(&vcpu->run->s.regs.fpc);
- if (cpu_has_vx())
- save_vx_regs((__vector128 *)&vcpu->run->s.regs.vrs);
- else
- save_fp_regs((freg_t *)&vcpu->run->s.regs.fprs);
+ kvm_s390_fpu_store(vcpu->run);
if (likely(!kvm_s390_pv_cpu_is_protected(vcpu)))
store_regs_fmt2(vcpu);
}
* switch in the run ioctl. Let's update our copies before we save
* it into the save area
*/
- fpu_stfpc(&vcpu->run->s.regs.fpc);
- if (cpu_has_vx())
- save_vx_regs((__vector128 *)&vcpu->run->s.regs.vrs);
- else
- save_fp_regs((freg_t *)&vcpu->run->s.regs.fprs);
+ kvm_s390_fpu_store(vcpu->run);
save_access_regs(vcpu->run->s.regs.acrs);
return kvm_s390_store_status_unloaded(vcpu, addr);
#include <asm/processor.h>
#include <asm/sclp.h>
+static inline void kvm_s390_fpu_store(struct kvm_run *run)
+{
+ fpu_stfpc(&run->s.regs.fpc);
+ if (cpu_has_vx())
+ save_vx_regs((__vector128 *)&run->s.regs.vrs);
+ else
+ save_fp_regs((freg_t *)&run->s.regs.fprs);
+}
+
+static inline void kvm_s390_fpu_load(struct kvm_run *run)
+{
+ fpu_lfpc_safe(&run->s.regs.fpc);
+ if (cpu_has_vx())
+ load_vx_regs((__vector128 *)&run->s.regs.vrs);
+ else
+ load_fp_regs((freg_t *)&run->s.regs.fprs);
+}
+
/* Transactional Memory Execution related macros */
#define IS_TE_ENABLED(vcpu) ((vcpu->arch.sie_block->ecb & ECB_TE))
#define TDB_FORMAT1 1