dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible
authorMichal Simek <michal.simek@amd.com>
Mon, 6 Nov 2023 11:37:47 +0000 (12:37 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 20 Dec 2023 15:15:00 +0000 (07:15 -0800)
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/d442d916204d26f82c1c3a924a4cdfb117960e1b.1699270661.git.michal.simek@amd.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/devicetree/bindings/riscv/cpus.yaml

index f392e367d673f5c2c8853379c1955b906211c41e..23646b684ea279b1962e555736683c906135f569 100644 (file)
@@ -32,6 +32,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - amd,mbv32
               - andestech,ax45mp
               - canaan,k210
               - sifive,bullet0