riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

Enable the minimal blocks required for booting the Renesas RZ/Five
SMARC EVK with initramfs.

Below are the blocks which are enabled:
- CPG
- CPU0
- DDR (memory regions)
- PINCTRL
- PLIC
- SCIF0

As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and
carrier [2] board DTSIs which enables almost all the blocks supported
by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually
enabling the blocks hence the aliases for ETH/I2C are deleted and rest
of the IP blocks are marked as disabled/deleted.

[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
[1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
[2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd0aa07c2729233aa896add60ce78e..b0ff5fbabb0c9a20613625644fa77ca4fc123b86 100644 (file)
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
 subdir-y += starfive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
 subdir-y += microchip
+subdir-y += renesas
 
 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
new file mode 100644 (file)
index 0000000..2d3f575
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
new file mode 100644 (file)
index 0000000..2aa8515
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/*
+ * DIP-Switch SW1 setting
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL      (0: uSD; 1: eMMC)
+ * SW1-3 : SW_ET0_EN_N         (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
+ * Please change below macros according to SW1 setting on the SoM
+ */
+#define SW_SW0_DEV_SEL 1
+#define SW_ET0_EN_N    1
+
+#include "r9a07g043f.dtsi"
+#include "rzfive-smarc-som.dtsi"
+#include "rzfive-smarc.dtsi"
+
+/ {
+       model = "Renesas SMARC EVK based on r9a07g043f01";
+       compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
+};

diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
new file mode 100644 (file)
index 0000000..45a182f
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK SOM
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
+
+/ {
+       aliases {
+               /delete-property/ ethernet0;
+               /delete-property/ ethernet1;
+       };
+
+       chosen {
+               bootargs = "ignore_loglevel";
+       };
+
+       /delete-node/opp-table-0;
+       /delete-node/thermal-zones;
+};
+
+&adc {
+       status = "disabled";
+};
+
+&dmac {
+       status = "disabled";
+};
+
+&eth0 {
+       status = "disabled";
+};
+
+&eth1 {
+       status = "disabled";
+};
+
+&ostm1 {
+       status = "disabled";
+};
+
+&ostm2 {
+       status = "disabled";
+};
+
+&sdhi0 {
+       status = "disabled";
+};
+
+&tsu {
+       status = "disabled";
+};
+
+&wdt0 {
+       status = "disabled";
+};

diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
new file mode 100644 (file)
index 0000000..e64f0e5
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK carrier board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc.dtsi>
+
+/ {
+       aliases {
+               /delete-property/ i2c0;
+               /delete-property/ i2c1;
+       };
+};
+
+&canfd {
+       status = "disabled";
+
+       channel0 {
+               status = "disabled";
+       };
+
+       channel1 {
+               status = "disabled";
+       };
+};
+
+&ehci0 {
+       status = "disabled";
+};
+
+&ehci1 {
+       status = "disabled";
+};
+
+&hsusb {
+       status = "disabled";
+};
+
+&i2c0 {
+       status = "disabled";
+};
+
+&i2c1 {
+       status = "disabled";
+};
+
+&ohci0 {
+       status = "disabled";
+};
+
+&ohci1 {
+       status = "disabled";
+};
+
+&phyrst {
+       status = "disabled";
+};
+
+&sdhi1 {
+       status = "disabled";
+};
+
+&snd_rzg2l {
+       status = "disabled";
+};
+
+&spi1 {
+       status = "disabled";
+};
+
+&ssi1 {
+       status = "disabled";
+};
+
+&usb0_vbus_otg {
+       status = "disabled";
+};
+
+&usb2_phy0 {
+       status = "disabled";
+};
+
+&usb2_phy1 {
+       status = "disabled";
+};
+
+&vccq_sdhi1 {
+       status = "disabled";
+};