+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * AMD ACP 6.2 Register Documentation
- *
- * Copyright 2022 Advanced Micro Devices, Inc.
- */
-
-#ifndef _acp_ip_OFFSET_HEADER
-#define _acp_ip_OFFSET_HEADER
-
-/* Registers from ACP_DMA block */
-#define ACP_DMA_CNTL_0 0x0000000
-#define ACP_DMA_CNTL_1 0x0000004
-#define ACP_DMA_CNTL_2 0x0000008
-#define ACP_DMA_CNTL_3 0x000000C
-#define ACP_DMA_CNTL_4 0x0000010
-#define ACP_DMA_CNTL_5 0x0000014
-#define ACP_DMA_CNTL_6 0x0000018
-#define ACP_DMA_CNTL_7 0x000001C
-#define ACP_DMA_DSCR_STRT_IDX_0 0x0000020
-#define ACP_DMA_DSCR_STRT_IDX_1 0x0000024
-#define ACP_DMA_DSCR_STRT_IDX_2 0x0000028
-#define ACP_DMA_DSCR_STRT_IDX_3 0x000002C
-#define ACP_DMA_DSCR_STRT_IDX_4 0x0000030
-#define ACP_DMA_DSCR_STRT_IDX_5 0x0000034
-#define ACP_DMA_DSCR_STRT_IDX_6 0x0000038
-#define ACP_DMA_DSCR_STRT_IDX_7 0x000003C
-#define ACP_DMA_DSCR_CNT_0 0x0000040
-#define ACP_DMA_DSCR_CNT_1 0x0000044
-#define ACP_DMA_DSCR_CNT_2 0x0000048
-#define ACP_DMA_DSCR_CNT_3 0x000004C
-#define ACP_DMA_DSCR_CNT_4 0x0000050
-#define ACP_DMA_DSCR_CNT_5 0x0000054
-#define ACP_DMA_DSCR_CNT_6 0x0000058
-#define ACP_DMA_DSCR_CNT_7 0x000005C
-#define ACP_DMA_PRIO_0 0x0000060
-#define ACP_DMA_PRIO_1 0x0000064
-#define ACP_DMA_PRIO_2 0x0000068
-#define ACP_DMA_PRIO_3 0x000006C
-#define ACP_DMA_PRIO_4 0x0000070
-#define ACP_DMA_PRIO_5 0x0000074
-#define ACP_DMA_PRIO_6 0x0000078
-#define ACP_DMA_PRIO_7 0x000007C
-#define ACP_DMA_CUR_DSCR_0 0x0000080
-#define ACP_DMA_CUR_DSCR_1 0x0000084
-#define ACP_DMA_CUR_DSCR_2 0x0000088
-#define ACP_DMA_CUR_DSCR_3 0x000008C
-#define ACP_DMA_CUR_DSCR_4 0x0000090
-#define ACP_DMA_CUR_DSCR_5 0x0000094
-#define ACP_DMA_CUR_DSCR_6 0x0000098
-#define ACP_DMA_CUR_DSCR_7 0x000009C
-#define ACP_DMA_CUR_TRANS_CNT_0 0x00000A0
-#define ACP_DMA_CUR_TRANS_CNT_1 0x00000A4
-#define ACP_DMA_CUR_TRANS_CNT_2 0x00000A8
-#define ACP_DMA_CUR_TRANS_CNT_3 0x00000AC
-#define ACP_DMA_CUR_TRANS_CNT_4 0x00000B0
-#define ACP_DMA_CUR_TRANS_CNT_5 0x00000B4
-#define ACP_DMA_CUR_TRANS_CNT_6 0x00000B8
-#define ACP_DMA_CUR_TRANS_CNT_7 0x00000BC
-#define ACP_DMA_ERR_STS_0 0x00000C0
-#define ACP_DMA_ERR_STS_1 0x00000C4
-#define ACP_DMA_ERR_STS_2 0x00000C8
-#define ACP_DMA_ERR_STS_3 0x00000CC
-#define ACP_DMA_ERR_STS_4 0x00000D0
-#define ACP_DMA_ERR_STS_5 0x00000D4
-#define ACP_DMA_ERR_STS_6 0x00000D8
-#define ACP_DMA_ERR_STS_7 0x00000DC
-#define ACP_DMA_DESC_BASE_ADDR 0x00000E0
-#define ACP_DMA_DESC_MAX_NUM_DSCR 0x00000E4
-#define ACP_DMA_CH_STS 0x00000E8
-#define ACP_DMA_CH_GROUP 0x00000EC
-#define ACP_DMA_CH_RST_STS 0x00000F0
-
-/* Registers from ACP_AXI2AXIATU block */
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C
-#define ACPAXI2AXI_ATU_CTRL 0x0000C40
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78
-#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C
-#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80
-
-/* Registers from ACP_CLKRST block */
-#define ACP_SOFT_RESET 0x0001000
-#define ACP_CONTROL 0x0001004
-#define ACP_STATUS 0x0001008
-#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010
-#define ACP_ZSC_DSP_CTRL 0x0001014
-#define ACP_ZSC_STS 0x0001018
-#define ACP_PGFSM_CONTROL 0x0001024
-#define ACP_PGFSM_STATUS 0x0001028
-#define ACP_CLKMUX_SEL 0x000102C
-
-/* Registers from ACP_AON block */
-#define ACP_PME_EN 0x0001400
-#define ACP_DEVICE_STATE 0x0001404
-#define AZ_DEVICE_STATE 0x0001408
-#define ACP_PIN_CONFIG 0x0001440
-#define ACP_PAD_PULLUP_CTRL 0x0001444
-#define ACP_PAD_PULLDOWN_CTRL 0x0001448
-#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C
-#define ACP_PAD_SCHMEN_CTRL 0x0001450
-#define ACP_SW_PAD_KEEPER_EN 0x0001454
-#define ACP_SW_WAKE_EN 0x0001458
-#define ACP_I2S_WAKE_EN 0x000145C
-#define ACP_SW1_WAKE_EN 0x0001460
-
-#define ACP_SW_I2S_ERROR_REASON 0x00018B4
-#define ACP_SW_POS_TRACK_I2S_TX_CTRL 0x00018B8
-#define ACP_SW_I2S_TX_DMA_POS 0x00018BC
-#define ACP_SW_POS_TRACK_BT_TX_CTRL 0x00018C0
-#define ACP_SW_BT_TX_DMA_POS 0x00018C4
-#define ACP_SW_POS_TRACK_HS_TX_CTRL 0x00018C8
-#define ACP_SW_HS_TX_DMA_POS 0x00018CC
-#define ACP_SW_POS_TRACK_I2S_RX_CTRL 0x00018D0
-#define ACP_SW_I2S_RX_DMA_POS 0x00018D4
-#define ACP_SW_POS_TRACK_BT_RX_CTRL 0x00018D8
-#define ACP_SW_BT_RX_DMA_POS 0x00018DC
-#define ACP_SW_POS_TRACK_HS_RX_CTRL 0x00018E0
-#define ACP_SW_HS_RX_DMA_POS 0x00018E4
-#define ACP_ERROR_INTR_MASK1 0X0001974
-#define ACP_ERROR_INTR_MASK2 0X0001978
-#define ACP_ERROR_INTR_MASK3 0X000197C
-
-/* Registers from ACP_P1_MISC block */
-#define ACP_EXTERNAL_INTR_ENB 0x0001A00
-#define ACP_EXTERNAL_INTR_CNTL 0x0001A04
-#define ACP_EXTERNAL_INTR_CNTL1 0x0001A08
-#define ACP_EXTERNAL_INTR_STAT 0x0001A0C
-#define ACP_EXTERNAL_INTR_STAT1 0x0001A10
-#define ACP_ERROR_STATUS 0x0001A4C
-#define ACP_P1_SW_I2S_ERROR_REASON 0x0001A50
-#define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x0001A6C
-#define ACP_P1_SW_I2S_TX_DMA_POS 0x0001A70
-#define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x0001A74
-#define ACP_P1_SW_I2S_RX_DMA_POS 0x0001A78
-#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C
-#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80
-#define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84
-#define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x0001A88
-#define ACP_P1_SW_BT_TX_DMA_POS 0x0001A8C
-#define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x0001A90
-#define ACP_P1_SW_HS_TX_DMA_POS 0x0001A94
-#define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x0001A98
-#define ACP_P1_SW_BT_RX_DMA_POS 0x0001A9C
-#define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x0001AA0
-#define ACP_P1_SW_HS_RX_DMA_POS 0x0001AA4
-#define ACP_ERROR_INTR_MASK4 0X0001AEC
-#define ACP_ERROR_INTR_MASK5 0X0001AF0
-
-/* Registers from ACP_AUDIO_BUFFERS block */
-#define ACP_I2S_RX_RINGBUFADDR 0x0002000
-#define ACP_I2S_RX_RINGBUFSIZE 0x0002004
-#define ACP_I2S_RX_LINKPOSITIONCNTR 0x0002008
-#define ACP_I2S_RX_FIFOADDR 0x000200C
-#define ACP_I2S_RX_FIFOSIZE 0x0002010
-#define ACP_I2S_RX_DMA_SIZE 0x0002014
-#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0002018
-#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x000201C
-#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x0002020
-#define ACP_I2S_TX_RINGBUFADDR 0x0002024
-#define ACP_I2S_TX_RINGBUFSIZE 0x0002028
-#define ACP_I2S_TX_LINKPOSITIONCNTR 0x000202C
-#define ACP_I2S_TX_FIFOADDR 0x0002030
-#define ACP_I2S_TX_FIFOSIZE 0x0002034
-#define ACP_I2S_TX_DMA_SIZE 0x0002038
-#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x000203C
-#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0002040
-#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x0002044
-#define ACP_BT_RX_RINGBUFADDR 0x0002048
-#define ACP_BT_RX_RINGBUFSIZE 0x000204C
-#define ACP_BT_RX_LINKPOSITIONCNTR 0x0002050
-#define ACP_BT_RX_FIFOADDR 0x0002054
-#define ACP_BT_RX_FIFOSIZE 0x0002058
-#define ACP_BT_RX_DMA_SIZE 0x000205C
-#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0002060
-#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x0002064
-#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x0002068
-#define ACP_BT_TX_RINGBUFADDR 0x000206C
-#define ACP_BT_TX_RINGBUFSIZE 0x0002070
-#define ACP_BT_TX_LINKPOSITIONCNTR 0x0002074
-#define ACP_BT_TX_FIFOADDR 0x0002078
-#define ACP_BT_TX_FIFOSIZE 0x000207C
-#define ACP_BT_TX_DMA_SIZE 0x0002080
-#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0002084
-#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x0002088
-#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x000208C
-#define ACP_HS_RX_RINGBUFADDR 0x0002090
-#define ACP_HS_RX_RINGBUFSIZE 0x0002094
-#define ACP_HS_RX_LINKPOSITIONCNTR 0x0002098
-#define ACP_HS_RX_FIFOADDR 0x000209C
-#define ACP_HS_RX_FIFOSIZE 0x00020A0
-#define ACP_HS_RX_DMA_SIZE 0x00020A4
-#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8
-#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x00020AC
-#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x00020B0
-#define ACP_HS_TX_RINGBUFADDR 0x00020B4
-#define ACP_HS_TX_RINGBUFSIZE 0x00020B8
-#define ACP_HS_TX_LINKPOSITIONCNTR 0x00020BC
-#define ACP_HS_TX_FIFOADDR 0x00020C0
-#define ACP_HS_TX_FIFOSIZE 0x00020C4
-#define ACP_HS_TX_DMA_SIZE 0x00020C8
-#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC
-#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x00020D0
-#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x00020D4
-#define ACP_AUDIO_RX_RINGBUFADDR ACP_I2S_RX_RINGBUFADDR
-#define ACP_AUDIO_RX_RINGBUFSIZE ACP_I2S_RX_RINGBUFSIZE
-#define ACP_AUDIO_RX_LINKPOSITIONCNTR ACP_I2S_RX_LINKPOSITIONCNTR
-#define ACP_AUDIO_RX_FIFOADDR ACP_I2S_RX_FIFOADDR
-#define ACP_AUDIO_RX_FIFOSIZE ACP_I2S_RX_FIFOSIZE
-#define ACP_AUDIO_RX_DMA_SIZE ACP_I2S_RX_DMA_SIZE
-#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH
-#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_I2S_RX_LINEARPOSITIONCNTR_LOW
-#define ACP_AUDIO_RX_INTR_WATERMARK_SIZE ACP_I2S_RX_INTR_WATERMARK_SIZE
-#define ACP_AUDIO_TX_RINGBUFADDR ACP_I2S_TX_RINGBUFADDR
-#define ACP_AUDIO_TX_RINGBUFSIZE ACP_I2S_TX_RINGBUFSIZE
-#define ACP_AUDIO_TX_LINKPOSITIONCNTR ACP_I2S_TX_LINKPOSITIONCNTR
-#define ACP_AUDIO_TX_FIFOADDR ACP_I2S_TX_FIFOADDR
-#define ACP_AUDIO_TX_FIFOSIZE ACP_I2S_TX_FIFOSIZE
-#define ACP_AUDIO_TX_DMA_SIZE ACP_I2S_TX_DMA_SIZE
-#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH
-#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_I2S_TX_LINEARPOSITIONCNTR_LOW
-#define ACP_AUDIO_TX_INTR_WATERMARK_SIZE ACP_I2S_TX_INTR_WATERMARK_SIZE
-
-/* Registers from ACP_I2S_TDM block */
-#define ACP_I2STDM_IER 0x0002400
-#define ACP_I2STDM_IRER 0x0002404
-#define ACP_I2STDM_RXFRMT 0x0002408
-#define ACP_I2STDM_ITER 0x000240C
-#define ACP_I2STDM_TXFRMT 0x0002410
-#define ACP_I2STDM0_MSTRCLKGEN 0x0002414
-#define ACP_I2STDM1_MSTRCLKGEN 0x0002418
-#define ACP_I2STDM2_MSTRCLKGEN 0x000241C
-#define ACP_I2STDM_REFCLKGEN 0x0002420
-
-/* Registers from ACP_BT_TDM block */
-#define ACP_BTTDM_IER 0x0002800
-#define ACP_BTTDM_IRER 0x0002804
-#define ACP_BTTDM_RXFRMT 0x0002808
-#define ACP_BTTDM_ITER 0x000280C
-#define ACP_BTTDM_TXFRMT 0x0002810
-#define ACP_HSTDM_IER 0x0002814
-#define ACP_HSTDM_IRER 0x0002818
-#define ACP_HSTDM_RXFRMT 0x000281C
-#define ACP_HSTDM_ITER 0x0002820
-#define ACP_HSTDM_TXFRMT 0x0002824
-
-/* Registers from ACP_WOV block */
-#define ACP_WOV_PDM_ENABLE 0x0002C04
-#define ACP_WOV_PDM_DMA_ENABLE 0x0002C08
-#define ACP_WOV_RX_RINGBUFADDR 0x0002C0C
-#define ACP_WOV_RX_RINGBUFSIZE 0x0002C10
-#define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14
-#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18
-#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C
-#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20
-#define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24
-#define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28
-#define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C
-#define ACP_WOV_PDM_VAD_CTRL 0x0002C30
-#define ACP_WOV_WAKE 0x0002C54
-#define ACP_WOV_BUFFER_STATUS 0x0002C58
-#define ACP_WOV_MISC_CTRL 0x0002C5C
-#define ACP_WOV_CLK_CTRL 0x0002C60
-#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64
-#define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68
-#define ACP_PDM_CLKDIV 0x0002C6C
-
-/* Registers from ACP_SW_SWCLK block */
-#define ACP_SW_EN 0x0003000
-#define ACP_SW_EN_STATUS 0x0003004
-#define ACP_SW_FRAMESIZE 0x0003008
-#define ACP_SW_SSP_COUNTER 0x000300C
-#define ACP_SW_AUDIO_TX_EN 0x0003010
-#define ACP_SW_AUDIO_TX_EN_STATUS 0x0003014
-#define ACP_SW_AUDIO_TX_FRAME_FORMAT 0x0003018
-#define ACP_SW_AUDIO_TX_SAMPLEINTERVAL 0x000301C
-#define ACP_SW_AUDIO_TX_HCTRL_DP0 0x0003020
-#define ACP_SW_AUDIO_TX_HCTRL_DP1 0x0003024
-#define ACP_SW_AUDIO_TX_HCTRL_DP2 0x0003028
-#define ACP_SW_AUDIO_TX_HCTRL_DP3 0x000302C
-#define ACP_SW_AUDIO_TX_OFFSET_DP0 0x0003030
-#define ACP_SW_AUDIO_TX_OFFSET_DP1 0x0003034
-#define ACP_SW_AUDIO_TX_OFFSET_DP2 0x0003038
-#define ACP_SW_AUDIO_TX_OFFSET_DP3 0x000303C
-#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP0 0x0003040
-#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP1 0x0003044
-#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP2 0x0003048
-#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP3 0x000304C
-#define ACP_SW_BT_TX_EN 0x0003050
-#define ACP_SW_BT_TX_EN_STATUS 0x0003054
-#define ACP_SW_BT_TX_FRAME_FORMAT 0x0003058
-#define ACP_SW_BT_TX_SAMPLEINTERVAL 0x000305C
-#define ACP_SW_BT_TX_HCTRL 0x0003060
-#define ACP_SW_BT_TX_OFFSET 0x0003064
-#define ACP_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003068
-#define ACP_SW_HEADSET_TX_EN 0x000306C
-#define ACP_SW_HEADSET_TX_EN_STATUS 0x0003070
-#define ACP_SW_HEADSET_TX_FRAME_FORMAT 0x0003074
-#define ACP_SW_HEADSET_TX_SAMPLEINTERVAL 0x0003078
-#define ACP_SW_HEADSET_TX_HCTRL 0x000307C
-#define ACP_SW_HEADSET_TX_OFFSET 0x0003080
-#define ACP_SW_HEADSET_TX_CHANNEL_ENABLE_DP0 0x0003084
-#define ACP_SW_AUDIO_RX_EN 0x0003088
-#define ACP_SW_AUDIO_RX_EN_STATUS 0x000308C
-#define ACP_SW_AUDIO_RX_FRAME_FORMAT 0x0003090
-#define ACP_SW_AUDIO_RX_SAMPLEINTERVAL 0x0003094
-#define ACP_SW_AUDIO_RX_HCTRL_DP0 0x0003098
-#define ACP_SW_AUDIO_RX_HCTRL_DP1 0x000309C
-#define ACP_SW_AUDIO_RX_HCTRL_DP2 0x0003100
-#define ACP_SW_AUDIO_RX_HCTRL_DP3 0x0003104
-#define ACP_SW_AUDIO_RX_OFFSET_DP0 0x0003108
-#define ACP_SW_AUDIO_RX_OFFSET_DP1 0x000310C
-#define ACP_SW_AUDIO_RX_OFFSET_DP2 0x0003110
-#define ACP_SW_AUDIO_RX_OFFSET_DP3 0x0003114
-#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP0 0x0003118
-#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP1 0x000311C
-#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP2 0x0003120
-#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP3 0x0003124
-#define ACP_SW_BT_RX_EN 0x0003128
-#define ACP_SW_BT_RX_EN_STATUS 0x000312C
-#define ACP_SW_BT_RX_FRAME_FORMAT 0x0003130
-#define ACP_SW_BT_RX_SAMPLEINTERVAL 0x0003134
-#define ACP_SW_BT_RX_HCTRL 0x0003138
-#define ACP_SW_BT_RX_OFFSET 0x000313C
-#define ACP_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003140
-#define ACP_SW_HEADSET_RX_EN 0x0003144
-#define ACP_SW_HEADSET_RX_EN_STATUS 0x0003148
-#define ACP_SW_HEADSET_RX_FRAME_FORMAT 0x000314C
-#define ACP_SW_HEADSET_RX_SAMPLEINTERVAL 0x0003150
-#define ACP_SW_HEADSET_RX_HCTRL 0x0003154
-#define ACP_SW_HEADSET_RX_OFFSET 0x0003158
-#define ACP_SW_HEADSET_RX_CHANNEL_ENABLE_DP0 0x000315C
-#define ACP_SW_BPT_PORT_EN 0x0003160
-#define ACP_SW_BPT_PORT_EN_STATUS 0x0003164
-#define ACP_SW_BPT_PORT_FRAME_FORMAT 0x0003168
-#define ACP_SW_BPT_PORT_SAMPLEINTERVAL 0x000316C
-#define ACP_SW_BPT_PORT_HCTRL 0x0003170
-#define ACP_SW_BPT_PORT_OFFSET 0x0003174
-#define ACP_SW_BPT_PORT_CHANNEL_ENABLE 0x0003178
-#define ACP_SW_BPT_PORT_FIRST_BYTE_ADDR 0x000317C
-#define ACP_SW_CLK_RESUME_CTRL 0x0003180
-#define ACP_SW_CLK_RESUME_DELAY_CNTR 0x0003184
-#define ACP_SW_BUS_RESET_CTRL 0x0003188
-#define ACP_SW_PRBS_ERR_STATUS 0x000318C
-#define SW_IMM_CMD_UPPER_WORD 0x0003230
-#define SW_IMM_CMD_LOWER_QWORD 0x0003234
-#define SW_IMM_RESP_UPPER_WORD 0x0003238
-#define SW_IMM_RESP_LOWER_QWORD 0x000323C
-#define SW_IMM_CMD_STS 0x0003240
-#define SW_BRA_BASE_ADDRESS 0x0003244
-#define SW_BRA_TRANSFER_SIZE 0x0003248
-#define SW_BRA_DMA_BUSY 0x000324C
-#define SW_BRA_RESP 0x0003250
-#define SW_BRA_RESP_FRAME_ADDR 0x0003254
-#define SW_BRA_CURRENT_TRANSFER_SIZE 0x0003258
-#define SW_STATE_CHANGE_STATUS_0TO7 0x000325C
-#define SW_STATE_CHANGE_STATUS_8TO11 0x0003260
-#define SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003264
-#define SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003268
-#define SW_CLK_FREQUENCY_CTRL 0x000326C
-#define SW_ERROR_INTR_MASK 0x0003270
-#define SW_PHY_TEST_MODE_DATA_OFF 0x0003274
-
-/* Registers from ACP_P1_AUDIO_BUFFERS block */
-#define ACP_P1_I2S_RX_RINGBUFADDR 0x0003A00
-#define ACP_P1_I2S_RX_RINGBUFSIZE 0x0003A04
-#define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x0003A08
-#define ACP_P1_I2S_RX_FIFOADDR 0x0003A0C
-#define ACP_P1_I2S_RX_FIFOSIZE 0x0003A10
-#define ACP_P1_I2S_RX_DMA_SIZE 0x0003A14
-#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18
-#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C
-#define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x0003A20
-#define ACP_P1_I2S_TX_RINGBUFADDR 0x0003A24
-#define ACP_P1_I2S_TX_RINGBUFSIZE 0x0003A28
-#define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x0003A2C
-#define ACP_P1_I2S_TX_FIFOADDR 0x0003A30
-#define ACP_P1_I2S_TX_FIFOSIZE 0x0003A34
-#define ACP_P1_I2S_TX_DMA_SIZE 0x0003A38
-#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C
-#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0003A40
-#define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x0003A44
-#define ACP_P1_BT_RX_RINGBUFADDR 0x0003A48
-#define ACP_P1_BT_RX_RINGBUFSIZE 0x0003A4C
-#define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x0003A50
-#define ACP_P1_BT_RX_FIFOADDR 0x0003A54
-#define ACP_P1_BT_RX_FIFOSIZE 0x0003A58
-#define ACP_P1_BT_RX_DMA_SIZE 0x0003A5C
-#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60
-#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x0003A64
-#define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x0003A68
-#define ACP_P1_BT_TX_RINGBUFADDR 0x0003A6C
-#define ACP_P1_BT_TX_RINGBUFSIZE 0x0003A70
-#define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x0003A74
-#define ACP_P1_BT_TX_FIFOADDR 0x0003A78
-#define ACP_P1_BT_TX_FIFOSIZE 0x0003A7C
-#define ACP_P1_BT_TX_DMA_SIZE 0x0003A80
-#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84
-#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x0003A88
-#define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x0003A8C
-#define ACP_P1_HS_RX_RINGBUFADDR 0x0003A90
-#define ACP_P1_HS_RX_RINGBUFSIZE 0x0003A94
-#define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x0003A98
-#define ACP_P1_HS_RX_FIFOADDR 0x0003A9C
-#define ACP_P1_HS_RX_FIFOSIZE 0x0003AA0
-#define ACP_P1_HS_RX_DMA_SIZE 0x0003AA4
-#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8
-#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC
-#define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x0003AB0
-#define ACP_P1_HS_TX_RINGBUFADDR 0x0003AB4
-#define ACP_P1_HS_TX_RINGBUFSIZE 0x0003AB8
-#define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x0003ABC
-#define ACP_P1_HS_TX_FIFOADDR 0x0003AC0
-#define ACP_P1_HS_TX_FIFOSIZE 0x0003AC4
-#define ACP_P1_HS_TX_DMA_SIZE 0x0003AC8
-#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC
-#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0
-#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x0003AD4
-#define ACP_P1_AUDIO_RX_RINGBUFADDR ACP_P1_I2S_RX_RINGBUFADDR
-#define ACP_P1_AUDIO_RX_RINGBUFSIZE ACP_P1_I2S_RX_RINGBUFSIZE
-#define ACP_P1_AUDIO_RX_LINKPOSITIONCNTR ACP_P1_I2S_RX_LINKPOSITIONCNTR
-#define ACP_P1_AUDIO_RX_FIFOADDR ACP_P1_I2S_RX_FIFOADDR
-#define ACP_P1_AUDIO_RX_FIFOSIZE ACP_P1_I2S_RX_FIFOSIZE
-#define ACP_P1_AUDIO_RX_DMA_SIZE ACP_P1_I2S_RX_DMA_SIZE
-#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH
-#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW
-#define ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE ACP_P1_I2S_RX_INTR_WATERMARK_SIZE
-#define ACP_P1_AUDIO_TX_RINGBUFADDR ACP_P1_I2S_TX_RINGBUFADDR
-#define ACP_P1_AUDIO_TX_RINGBUFSIZE ACP_P1_I2S_TX_RINGBUFSIZE
-#define ACP_P1_AUDIO_TX_LINKPOSITIONCNTR ACP_P1_I2S_TX_LINKPOSITIONCNTR
-#define ACP_P1_AUDIO_TX_FIFOADDR ACP_P1_I2S_TX_FIFOADDR
-#define ACP_P1_AUDIO_TX_FIFOSIZE ACP_P1_I2S_TX_FIFOSIZE
-#define ACP_P1_AUDIO_TX_DMA_SIZE ACP_P1_I2S_TX_DMA_SIZE
-#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH
-#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW
-#define ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE ACP_P1_I2S_TX_INTR_WATERMARK_SIZE
-
-/* Registers from ACP_P1_SW_SWCLK block */
-#define ACP_P1_SW_EN 0x0003C00
-#define ACP_P1_SW_EN_STATUS 0x0003C04
-#define ACP_P1_SW_FRAMESIZE 0x0003C08
-#define ACP_P1_SW_SSP_COUNTER 0x0003C0C
-#define ACP_P1_SW_BT_TX_EN 0x0003C50
-#define ACP_P1_SW_BT_TX_EN_STATUS 0x0003C54
-#define ACP_P1_SW_BT_TX_FRAME_FORMAT 0x0003C58
-#define ACP_P1_SW_BT_TX_SAMPLEINTERVAL 0x0003C5C
-#define ACP_P1_SW_BT_TX_HCTRL 0x0003C60
-#define ACP_P1_SW_BT_TX_OFFSET 0x0003C64
-#define ACP_P1_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003C68
-#define ACP_P1_SW_BT_RX_EN 0x0003D28
-#define ACP_P1_SW_BT_RX_EN_STATUS 0x0003D2C
-#define ACP_P1_SW_BT_RX_FRAME_FORMAT 0x0003D30
-#define ACP_P1_SW_BT_RX_SAMPLEINTERVAL 0x0003D34
-#define ACP_P1_SW_BT_RX_HCTRL 0x0003D38
-#define ACP_P1_SW_BT_RX_OFFSET 0x0003D3C
-#define ACP_P1_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003D40
-#define ACP_P1_SW_BPT_PORT_EN 0x0003D60
-#define ACP_P1_SW_BPT_PORT_EN_STATUS 0x0003D64
-#define ACP_P1_SW_BPT_PORT_FRAME_FORMAT 0x0003D68
-#define ACP_P1_SW_BPT_PORT_SAMPLEINTERVAL 0x0003D6C
-#define ACP_P1_SW_BPT_PORT_HCTRL 0x0003D70
-#define ACP_P1_SW_BPT_PORT_OFFSET 0x0003D74
-#define ACP_P1_SW_BPT_PORT_CHANNEL_ENABLE 0x0003D78
-#define ACP_P1_SW_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C
-#define ACP_P1_SW_CLK_RESUME_CTRL 0x0003D80
-#define ACP_P1_SW_CLK_RESUME_DELAY_CNTR 0x0003D84
-#define ACP_P1_SW_BUS_RESET_CTRL 0x0003D88
-#define ACP_P1_SW_PRBS_ERR_STATUS 0x0003D8C
-
-/* Registers from ACP_P1_SW_ACLK block */
-#define P1_SW_CORB_BASE_ADDRESS 0x0003E00
-#define P1_SW_CORB_WRITE_POINTER 0x0003E04
-#define P1_SW_CORB_READ_POINTER 0x0003E08
-#define P1_SW_CORB_CONTROL 0x0003E0C
-#define P1_SW_CORB_SIZE 0x0003E14
-#define P1_SW_RIRB_BASE_ADDRESS 0x0003E18
-#define P1_SW_RIRB_WRITE_POINTER 0x0003E1C
-#define P1_SW_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20
-#define P1_SW_RIRB_CONTROL 0x0003E24
-#define P1_SW_RIRB_SIZE 0x0003E28
-#define P1_SW_RIRB_FIFO_MIN_THDL 0x0003E2C
-#define P1_SW_IMM_CMD_UPPER_WORD 0x0003E30
-#define P1_SW_IMM_CMD_LOWER_QWORD 0x0003E34
-#define P1_SW_IMM_RESP_UPPER_WORD 0x0003E38
-#define P1_SW_IMM_RESP_LOWER_QWORD 0x0003E3C
-#define P1_SW_IMM_CMD_STS 0x0003E40
-#define P1_SW_BRA_BASE_ADDRESS 0x0003E44
-#define P1_SW_BRA_TRANSFER_SIZE 0x0003E48
-#define P1_SW_BRA_DMA_BUSY 0x0003E4C
-#define P1_SW_BRA_RESP 0x0003E50
-#define P1_SW_BRA_RESP_FRAME_ADDR 0x0003E54
-#define P1_SW_BRA_CURRENT_TRANSFER_SIZE 0x0003E58
-#define P1_SW_STATE_CHANGE_STATUS_0TO7 0x0003E5C
-#define P1_SW_STATE_CHANGE_STATUS_8TO11 0x0003E60
-#define P1_SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003E64
-#define P1_SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003E68
-#define P1_SW_CLK_FREQUENCY_CTRL 0x0003E6C
-#define P1_SW_ERROR_INTR_MASK 0x0003E70
-#define P1_SW_PHY_TEST_MODE_DATA_OFF 0x0003E74
-
-/* Registers from ACP_SCRATCH block */
-#define ACP_SCRATCH_REG_0 0x0010000
-#define ACP_SCRATCH_REG_1 0x0010004
-#define ACP_SCRATCH_REG_2 0x0010008
-#define ACP_SCRATCH_REG_3 0x001000C
-#define ACP_SCRATCH_REG_4 0x0010010
-#define ACP_SCRATCH_REG_5 0x0010014
-#define ACP_SCRATCH_REG_6 0x0010018
-#define ACP_SCRATCH_REG_7 0x001001C
-#define ACP_SCRATCH_REG_8 0x0010020
-#define ACP_SCRATCH_REG_9 0x0010024
-#define ACP_SCRATCH_REG_10 0x0010028
-#define ACP_SCRATCH_REG_11 0x001002C
-#define ACP_SCRATCH_REG_12 0x0010030
-#define ACP_SCRATCH_REG_13 0x0010034
-#define ACP_SCRATCH_REG_14 0x0010038
-#define ACP_SCRATCH_REG_15 0x001003C
-#define ACP_SCRATCH_REG_16 0x0010040
-#define ACP_SCRATCH_REG_17 0x0010044
-#define ACP_SCRATCH_REG_18 0x0010048
-#define ACP_SCRATCH_REG_19 0x001004C
-#define ACP_SCRATCH_REG_20 0x0010050
-#define ACP_SCRATCH_REG_21 0x0010054
-#define ACP_SCRATCH_REG_22 0x0010058
-#define ACP_SCRATCH_REG_23 0x001005C
-#define ACP_SCRATCH_REG_24 0x0010060
-#define ACP_SCRATCH_REG_25 0x0010064
-#define ACP_SCRATCH_REG_26 0x0010068
-#define ACP_SCRATCH_REG_27 0x001006C
-#define ACP_SCRATCH_REG_28 0x0010070
-#define ACP_SCRATCH_REG_29 0x0010074
-#define ACP_SCRATCH_REG_30 0x0010078
-#define ACP_SCRATCH_REG_31 0x001007C
-#define ACP_SCRATCH_REG_32 0x0010080
-#define ACP_SCRATCH_REG_33 0x0010084
-#define ACP_SCRATCH_REG_34 0x0010088
-#define ACP_SCRATCH_REG_35 0x001008C
-#define ACP_SCRATCH_REG_36 0x0010090
-#define ACP_SCRATCH_REG_37 0x0010094
-#define ACP_SCRATCH_REG_38 0x0010098
-#define ACP_SCRATCH_REG_39 0x001009C
-#define ACP_SCRATCH_REG_40 0x00100A0
-#define ACP_SCRATCH_REG_41 0x00100A4
-#define ACP_SCRATCH_REG_42 0x00100A8
-#define ACP_SCRATCH_REG_43 0x00100AC
-#define ACP_SCRATCH_REG_44 0x00100B0
-#define ACP_SCRATCH_REG_45 0x00100B4
-#define ACP_SCRATCH_REG_46 0x00100B8
-#define ACP_SCRATCH_REG_47 0x00100BC
-#define ACP_SCRATCH_REG_48 0x00100C0
-#define ACP_SCRATCH_REG_49 0x00100C4
-#define ACP_SCRATCH_REG_50 0x00100C8
-#define ACP_SCRATCH_REG_51 0x00100CC
-#define ACP_SCRATCH_REG_52 0x00100D0
-#define ACP_SCRATCH_REG_53 0x00100D4
-#define ACP_SCRATCH_REG_54 0x00100D8
-#define ACP_SCRATCH_REG_55 0x00100DC
-#define ACP_SCRATCH_REG_56 0x00100E0
-#define ACP_SCRATCH_REG_57 0x00100E4
-#define ACP_SCRATCH_REG_58 0x00100E8
-#define ACP_SCRATCH_REG_59 0x00100EC
-#define ACP_SCRATCH_REG_60 0x00100F0
-#define ACP_SCRATCH_REG_61 0x00100F4
-#define ACP_SCRATCH_REG_62 0x00100F8
-#define ACP_SCRATCH_REG_63 0x00100FC
-#define ACP_SCRATCH_REG_64 0x0010100
-#define ACP_SCRATCH_REG_65 0x0010104
-#define ACP_SCRATCH_REG_66 0x0010108
-#define ACP_SCRATCH_REG_67 0x001010C
-#define ACP_SCRATCH_REG_68 0x0010110
-#define ACP_SCRATCH_REG_69 0x0010114
-#define ACP_SCRATCH_REG_70 0x0010118
-#define ACP_SCRATCH_REG_71 0x001011C
-#define ACP_SCRATCH_REG_72 0x0010120
-#define ACP_SCRATCH_REG_73 0x0010124
-#define ACP_SCRATCH_REG_74 0x0010128
-#define ACP_SCRATCH_REG_75 0x001012C
-#define ACP_SCRATCH_REG_76 0x0010130
-#define ACP_SCRATCH_REG_77 0x0010134
-#define ACP_SCRATCH_REG_78 0x0010138
-#define ACP_SCRATCH_REG_79 0x001013C
-#define ACP_SCRATCH_REG_80 0x0010140
-#define ACP_SCRATCH_REG_81 0x0010144
-#define ACP_SCRATCH_REG_82 0x0010148
-#define ACP_SCRATCH_REG_83 0x001014C
-#define ACP_SCRATCH_REG_84 0x0010150
-#define ACP_SCRATCH_REG_85 0x0010154
-#define ACP_SCRATCH_REG_86 0x0010158
-#define ACP_SCRATCH_REG_87 0x001015C
-#define ACP_SCRATCH_REG_88 0x0010160
-#define ACP_SCRATCH_REG_89 0x0010164
-#define ACP_SCRATCH_REG_90 0x0010168
-#define ACP_SCRATCH_REG_91 0x001016C
-#define ACP_SCRATCH_REG_92 0x0010170
-#define ACP_SCRATCH_REG_93 0x0010174
-#define ACP_SCRATCH_REG_94 0x0010178
-#define ACP_SCRATCH_REG_95 0x001017C
-#define ACP_SCRATCH_REG_96 0x0010180
-#define ACP_SCRATCH_REG_97 0x0010184
-#define ACP_SCRATCH_REG_98 0x0010188
-#define ACP_SCRATCH_REG_99 0x001018C
-#define ACP_SCRATCH_REG_100 0x0010190
-#define ACP_SCRATCH_REG_101 0x0010194
-#define ACP_SCRATCH_REG_102 0x0010198
-#define ACP_SCRATCH_REG_103 0x001019C
-#define ACP_SCRATCH_REG_104 0x00101A0
-#define ACP_SCRATCH_REG_105 0x00101A4
-#define ACP_SCRATCH_REG_106 0x00101A8
-#define ACP_SCRATCH_REG_107 0x00101AC
-#define ACP_SCRATCH_REG_108 0x00101B0
-#define ACP_SCRATCH_REG_109 0x00101B4
-#define ACP_SCRATCH_REG_110 0x00101B8
-#define ACP_SCRATCH_REG_111 0x00101BC
-#define ACP_SCRATCH_REG_112 0x00101C0
-#define ACP_SCRATCH_REG_113 0x00101C4
-#define ACP_SCRATCH_REG_114 0x00101C8
-#define ACP_SCRATCH_REG_115 0x00101CC
-#define ACP_SCRATCH_REG_116 0x00101D0
-#define ACP_SCRATCH_REG_117 0x00101D4
-#define ACP_SCRATCH_REG_118 0x00101D8
-#define ACP_SCRATCH_REG_119 0x00101DC
-#define ACP_SCRATCH_REG_120 0x00101E0
-#define ACP_SCRATCH_REG_121 0x00101E4
-#define ACP_SCRATCH_REG_122 0x00101E8
-#define ACP_SCRATCH_REG_123 0x00101EC
-#define ACP_SCRATCH_REG_124 0x00101F0
-#define ACP_SCRATCH_REG_125 0x00101F4
-#define ACP_SCRATCH_REG_126 0x00101F8
-#define ACP_SCRATCH_REG_127 0x00101FC
-#define ACP_SCRATCH_REG_128 0x0010200
-#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * AMD ACP 6.3 Register Documentation
+ *
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ */
+
+#ifndef _acp_ip_OFFSET_HEADER
+#define _acp_ip_OFFSET_HEADER
+
+/* Registers from ACP_DMA block */
+#define ACP_DMA_CNTL_0 0x0000000
+#define ACP_DMA_CNTL_1 0x0000004
+#define ACP_DMA_CNTL_2 0x0000008
+#define ACP_DMA_CNTL_3 0x000000C
+#define ACP_DMA_CNTL_4 0x0000010
+#define ACP_DMA_CNTL_5 0x0000014
+#define ACP_DMA_CNTL_6 0x0000018
+#define ACP_DMA_CNTL_7 0x000001C
+#define ACP_DMA_DSCR_STRT_IDX_0 0x0000020
+#define ACP_DMA_DSCR_STRT_IDX_1 0x0000024
+#define ACP_DMA_DSCR_STRT_IDX_2 0x0000028
+#define ACP_DMA_DSCR_STRT_IDX_3 0x000002C
+#define ACP_DMA_DSCR_STRT_IDX_4 0x0000030
+#define ACP_DMA_DSCR_STRT_IDX_5 0x0000034
+#define ACP_DMA_DSCR_STRT_IDX_6 0x0000038
+#define ACP_DMA_DSCR_STRT_IDX_7 0x000003C
+#define ACP_DMA_DSCR_CNT_0 0x0000040
+#define ACP_DMA_DSCR_CNT_1 0x0000044
+#define ACP_DMA_DSCR_CNT_2 0x0000048
+#define ACP_DMA_DSCR_CNT_3 0x000004C
+#define ACP_DMA_DSCR_CNT_4 0x0000050
+#define ACP_DMA_DSCR_CNT_5 0x0000054
+#define ACP_DMA_DSCR_CNT_6 0x0000058
+#define ACP_DMA_DSCR_CNT_7 0x000005C
+#define ACP_DMA_PRIO_0 0x0000060
+#define ACP_DMA_PRIO_1 0x0000064
+#define ACP_DMA_PRIO_2 0x0000068
+#define ACP_DMA_PRIO_3 0x000006C
+#define ACP_DMA_PRIO_4 0x0000070
+#define ACP_DMA_PRIO_5 0x0000074
+#define ACP_DMA_PRIO_6 0x0000078
+#define ACP_DMA_PRIO_7 0x000007C
+#define ACP_DMA_CUR_DSCR_0 0x0000080
+#define ACP_DMA_CUR_DSCR_1 0x0000084
+#define ACP_DMA_CUR_DSCR_2 0x0000088
+#define ACP_DMA_CUR_DSCR_3 0x000008C
+#define ACP_DMA_CUR_DSCR_4 0x0000090
+#define ACP_DMA_CUR_DSCR_5 0x0000094
+#define ACP_DMA_CUR_DSCR_6 0x0000098
+#define ACP_DMA_CUR_DSCR_7 0x000009C
+#define ACP_DMA_CUR_TRANS_CNT_0 0x00000A0
+#define ACP_DMA_CUR_TRANS_CNT_1 0x00000A4
+#define ACP_DMA_CUR_TRANS_CNT_2 0x00000A8
+#define ACP_DMA_CUR_TRANS_CNT_3 0x00000AC
+#define ACP_DMA_CUR_TRANS_CNT_4 0x00000B0
+#define ACP_DMA_CUR_TRANS_CNT_5 0x00000B4
+#define ACP_DMA_CUR_TRANS_CNT_6 0x00000B8
+#define ACP_DMA_CUR_TRANS_CNT_7 0x00000BC
+#define ACP_DMA_ERR_STS_0 0x00000C0
+#define ACP_DMA_ERR_STS_1 0x00000C4
+#define ACP_DMA_ERR_STS_2 0x00000C8
+#define ACP_DMA_ERR_STS_3 0x00000CC
+#define ACP_DMA_ERR_STS_4 0x00000D0
+#define ACP_DMA_ERR_STS_5 0x00000D4
+#define ACP_DMA_ERR_STS_6 0x00000D8
+#define ACP_DMA_ERR_STS_7 0x00000DC
+#define ACP_DMA_DESC_BASE_ADDR 0x00000E0
+#define ACP_DMA_DESC_MAX_NUM_DSCR 0x00000E4
+#define ACP_DMA_CH_STS 0x00000E8
+#define ACP_DMA_CH_GROUP 0x00000EC
+#define ACP_DMA_CH_RST_STS 0x00000F0
+
+/* Registers from ACP_AXI2AXIATU block */
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C
+#define ACPAXI2AXI_ATU_CTRL 0x0000C40
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80
+
+/* Registers from ACP_CLKRST block */
+#define ACP_SOFT_RESET 0x0001000
+#define ACP_CONTROL 0x0001004
+#define ACP_STATUS 0x0001008
+#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010
+#define ACP_ZSC_DSP_CTRL 0x0001014
+#define ACP_ZSC_STS 0x0001018
+#define ACP_PGFSM_CONTROL 0x0001024
+#define ACP_PGFSM_STATUS 0x0001028
+#define ACP_CLKMUX_SEL 0x000102C
+
+/* Registers from ACP_AON block */
+#define ACP_PME_EN 0x0001400
+#define ACP_DEVICE_STATE 0x0001404
+#define AZ_DEVICE_STATE 0x0001408
+#define ACP_PIN_CONFIG 0x0001440
+#define ACP_PAD_PULLUP_CTRL 0x0001444
+#define ACP_PAD_PULLDOWN_CTRL 0x0001448
+#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C
+#define ACP_PAD_SCHMEN_CTRL 0x0001450
+#define ACP_SW_PAD_KEEPER_EN 0x0001454
+#define ACP_SW_WAKE_EN 0x0001458
+#define ACP_I2S_WAKE_EN 0x000145C
+#define ACP_SW1_WAKE_EN 0x0001460
+
+#define ACP_SW_I2S_ERROR_REASON 0x00018B4
+#define ACP_SW_POS_TRACK_I2S_TX_CTRL 0x00018B8
+#define ACP_SW_I2S_TX_DMA_POS 0x00018BC
+#define ACP_SW_POS_TRACK_BT_TX_CTRL 0x00018C0
+#define ACP_SW_BT_TX_DMA_POS 0x00018C4
+#define ACP_SW_POS_TRACK_HS_TX_CTRL 0x00018C8
+#define ACP_SW_HS_TX_DMA_POS 0x00018CC
+#define ACP_SW_POS_TRACK_I2S_RX_CTRL 0x00018D0
+#define ACP_SW_I2S_RX_DMA_POS 0x00018D4
+#define ACP_SW_POS_TRACK_BT_RX_CTRL 0x00018D8
+#define ACP_SW_BT_RX_DMA_POS 0x00018DC
+#define ACP_SW_POS_TRACK_HS_RX_CTRL 0x00018E0
+#define ACP_SW_HS_RX_DMA_POS 0x00018E4
+#define ACP_ERROR_INTR_MASK1 0X0001974
+#define ACP_ERROR_INTR_MASK2 0X0001978
+#define ACP_ERROR_INTR_MASK3 0X000197C
+
+/* Registers from ACP_P1_MISC block */
+#define ACP_EXTERNAL_INTR_ENB 0x0001A00
+#define ACP_EXTERNAL_INTR_CNTL 0x0001A04
+#define ACP_EXTERNAL_INTR_CNTL1 0x0001A08
+#define ACP_EXTERNAL_INTR_STAT 0x0001A0C
+#define ACP_EXTERNAL_INTR_STAT1 0x0001A10
+#define ACP_ERROR_STATUS 0x0001A4C
+#define ACP_P1_SW_I2S_ERROR_REASON 0x0001A50
+#define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x0001A6C
+#define ACP_P1_SW_I2S_TX_DMA_POS 0x0001A70
+#define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x0001A74
+#define ACP_P1_SW_I2S_RX_DMA_POS 0x0001A78
+#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C
+#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80
+#define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84
+#define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x0001A88
+#define ACP_P1_SW_BT_TX_DMA_POS 0x0001A8C
+#define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x0001A90
+#define ACP_P1_SW_HS_TX_DMA_POS 0x0001A94
+#define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x0001A98
+#define ACP_P1_SW_BT_RX_DMA_POS 0x0001A9C
+#define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x0001AA0
+#define ACP_P1_SW_HS_RX_DMA_POS 0x0001AA4
+#define ACP_ERROR_INTR_MASK4 0X0001AEC
+#define ACP_ERROR_INTR_MASK5 0X0001AF0
+
+/* Registers from ACP_AUDIO_BUFFERS block */
+#define ACP_I2S_RX_RINGBUFADDR 0x0002000
+#define ACP_I2S_RX_RINGBUFSIZE 0x0002004
+#define ACP_I2S_RX_LINKPOSITIONCNTR 0x0002008
+#define ACP_I2S_RX_FIFOADDR 0x000200C
+#define ACP_I2S_RX_FIFOSIZE 0x0002010
+#define ACP_I2S_RX_DMA_SIZE 0x0002014
+#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0002018
+#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x000201C
+#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x0002020
+#define ACP_I2S_TX_RINGBUFADDR 0x0002024
+#define ACP_I2S_TX_RINGBUFSIZE 0x0002028
+#define ACP_I2S_TX_LINKPOSITIONCNTR 0x000202C
+#define ACP_I2S_TX_FIFOADDR 0x0002030
+#define ACP_I2S_TX_FIFOSIZE 0x0002034
+#define ACP_I2S_TX_DMA_SIZE 0x0002038
+#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x000203C
+#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0002040
+#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x0002044
+#define ACP_BT_RX_RINGBUFADDR 0x0002048
+#define ACP_BT_RX_RINGBUFSIZE 0x000204C
+#define ACP_BT_RX_LINKPOSITIONCNTR 0x0002050
+#define ACP_BT_RX_FIFOADDR 0x0002054
+#define ACP_BT_RX_FIFOSIZE 0x0002058
+#define ACP_BT_RX_DMA_SIZE 0x000205C
+#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0002060
+#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x0002064
+#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x0002068
+#define ACP_BT_TX_RINGBUFADDR 0x000206C
+#define ACP_BT_TX_RINGBUFSIZE 0x0002070
+#define ACP_BT_TX_LINKPOSITIONCNTR 0x0002074
+#define ACP_BT_TX_FIFOADDR 0x0002078
+#define ACP_BT_TX_FIFOSIZE 0x000207C
+#define ACP_BT_TX_DMA_SIZE 0x0002080
+#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0002084
+#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x0002088
+#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x000208C
+#define ACP_HS_RX_RINGBUFADDR 0x0002090
+#define ACP_HS_RX_RINGBUFSIZE 0x0002094
+#define ACP_HS_RX_LINKPOSITIONCNTR 0x0002098
+#define ACP_HS_RX_FIFOADDR 0x000209C
+#define ACP_HS_RX_FIFOSIZE 0x00020A0
+#define ACP_HS_RX_DMA_SIZE 0x00020A4
+#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8
+#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x00020AC
+#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x00020B0
+#define ACP_HS_TX_RINGBUFADDR 0x00020B4
+#define ACP_HS_TX_RINGBUFSIZE 0x00020B8
+#define ACP_HS_TX_LINKPOSITIONCNTR 0x00020BC
+#define ACP_HS_TX_FIFOADDR 0x00020C0
+#define ACP_HS_TX_FIFOSIZE 0x00020C4
+#define ACP_HS_TX_DMA_SIZE 0x00020C8
+#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC
+#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x00020D0
+#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x00020D4
+#define ACP_AUDIO_RX_RINGBUFADDR ACP_I2S_RX_RINGBUFADDR
+#define ACP_AUDIO_RX_RINGBUFSIZE ACP_I2S_RX_RINGBUFSIZE
+#define ACP_AUDIO_RX_LINKPOSITIONCNTR ACP_I2S_RX_LINKPOSITIONCNTR
+#define ACP_AUDIO_RX_FIFOADDR ACP_I2S_RX_FIFOADDR
+#define ACP_AUDIO_RX_FIFOSIZE ACP_I2S_RX_FIFOSIZE
+#define ACP_AUDIO_RX_DMA_SIZE ACP_I2S_RX_DMA_SIZE
+#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH
+#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_I2S_RX_LINEARPOSITIONCNTR_LOW
+#define ACP_AUDIO_RX_INTR_WATERMARK_SIZE ACP_I2S_RX_INTR_WATERMARK_SIZE
+#define ACP_AUDIO_TX_RINGBUFADDR ACP_I2S_TX_RINGBUFADDR
+#define ACP_AUDIO_TX_RINGBUFSIZE ACP_I2S_TX_RINGBUFSIZE
+#define ACP_AUDIO_TX_LINKPOSITIONCNTR ACP_I2S_TX_LINKPOSITIONCNTR
+#define ACP_AUDIO_TX_FIFOADDR ACP_I2S_TX_FIFOADDR
+#define ACP_AUDIO_TX_FIFOSIZE ACP_I2S_TX_FIFOSIZE
+#define ACP_AUDIO_TX_DMA_SIZE ACP_I2S_TX_DMA_SIZE
+#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH
+#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_I2S_TX_LINEARPOSITIONCNTR_LOW
+#define ACP_AUDIO_TX_INTR_WATERMARK_SIZE ACP_I2S_TX_INTR_WATERMARK_SIZE
+
+/* Registers from ACP_I2S_TDM block */
+#define ACP_I2STDM_IER 0x0002400
+#define ACP_I2STDM_IRER 0x0002404
+#define ACP_I2STDM_RXFRMT 0x0002408
+#define ACP_I2STDM_ITER 0x000240C
+#define ACP_I2STDM_TXFRMT 0x0002410
+#define ACP_I2STDM0_MSTRCLKGEN 0x0002414
+#define ACP_I2STDM1_MSTRCLKGEN 0x0002418
+#define ACP_I2STDM2_MSTRCLKGEN 0x000241C
+#define ACP_I2STDM_REFCLKGEN 0x0002420
+
+/* Registers from ACP_BT_TDM block */
+#define ACP_BTTDM_IER 0x0002800
+#define ACP_BTTDM_IRER 0x0002804
+#define ACP_BTTDM_RXFRMT 0x0002808
+#define ACP_BTTDM_ITER 0x000280C
+#define ACP_BTTDM_TXFRMT 0x0002810
+#define ACP_HSTDM_IER 0x0002814
+#define ACP_HSTDM_IRER 0x0002818
+#define ACP_HSTDM_RXFRMT 0x000281C
+#define ACP_HSTDM_ITER 0x0002820
+#define ACP_HSTDM_TXFRMT 0x0002824
+
+/* Registers from ACP_WOV block */
+#define ACP_WOV_PDM_ENABLE 0x0002C04
+#define ACP_WOV_PDM_DMA_ENABLE 0x0002C08
+#define ACP_WOV_RX_RINGBUFADDR 0x0002C0C
+#define ACP_WOV_RX_RINGBUFSIZE 0x0002C10
+#define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14
+#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18
+#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C
+#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20
+#define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24
+#define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28
+#define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C
+#define ACP_WOV_PDM_VAD_CTRL 0x0002C30
+#define ACP_WOV_WAKE 0x0002C54
+#define ACP_WOV_BUFFER_STATUS 0x0002C58
+#define ACP_WOV_MISC_CTRL 0x0002C5C
+#define ACP_WOV_CLK_CTRL 0x0002C60
+#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64
+#define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68
+#define ACP_PDM_CLKDIV 0x0002C6C
+
+/* Registers from ACP_SW_SWCLK block */
+#define ACP_SW_EN 0x0003000
+#define ACP_SW_EN_STATUS 0x0003004
+#define ACP_SW_FRAMESIZE 0x0003008
+#define ACP_SW_SSP_COUNTER 0x000300C
+#define ACP_SW_AUDIO_TX_EN 0x0003010
+#define ACP_SW_AUDIO_TX_EN_STATUS 0x0003014
+#define ACP_SW_AUDIO_TX_FRAME_FORMAT 0x0003018
+#define ACP_SW_AUDIO_TX_SAMPLEINTERVAL 0x000301C
+#define ACP_SW_AUDIO_TX_HCTRL_DP0 0x0003020
+#define ACP_SW_AUDIO_TX_HCTRL_DP1 0x0003024
+#define ACP_SW_AUDIO_TX_HCTRL_DP2 0x0003028
+#define ACP_SW_AUDIO_TX_HCTRL_DP3 0x000302C
+#define ACP_SW_AUDIO_TX_OFFSET_DP0 0x0003030
+#define ACP_SW_AUDIO_TX_OFFSET_DP1 0x0003034
+#define ACP_SW_AUDIO_TX_OFFSET_DP2 0x0003038
+#define ACP_SW_AUDIO_TX_OFFSET_DP3 0x000303C
+#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP0 0x0003040
+#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP1 0x0003044
+#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP2 0x0003048
+#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP3 0x000304C
+#define ACP_SW_BT_TX_EN 0x0003050
+#define ACP_SW_BT_TX_EN_STATUS 0x0003054
+#define ACP_SW_BT_TX_FRAME_FORMAT 0x0003058
+#define ACP_SW_BT_TX_SAMPLEINTERVAL 0x000305C
+#define ACP_SW_BT_TX_HCTRL 0x0003060
+#define ACP_SW_BT_TX_OFFSET 0x0003064
+#define ACP_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003068
+#define ACP_SW_HEADSET_TX_EN 0x000306C
+#define ACP_SW_HEADSET_TX_EN_STATUS 0x0003070
+#define ACP_SW_HEADSET_TX_FRAME_FORMAT 0x0003074
+#define ACP_SW_HEADSET_TX_SAMPLEINTERVAL 0x0003078
+#define ACP_SW_HEADSET_TX_HCTRL 0x000307C
+#define ACP_SW_HEADSET_TX_OFFSET 0x0003080
+#define ACP_SW_HEADSET_TX_CHANNEL_ENABLE_DP0 0x0003084
+#define ACP_SW_AUDIO_RX_EN 0x0003088
+#define ACP_SW_AUDIO_RX_EN_STATUS 0x000308C
+#define ACP_SW_AUDIO_RX_FRAME_FORMAT 0x0003090
+#define ACP_SW_AUDIO_RX_SAMPLEINTERVAL 0x0003094
+#define ACP_SW_AUDIO_RX_HCTRL_DP0 0x0003098
+#define ACP_SW_AUDIO_RX_HCTRL_DP1 0x000309C
+#define ACP_SW_AUDIO_RX_HCTRL_DP2 0x0003100
+#define ACP_SW_AUDIO_RX_HCTRL_DP3 0x0003104
+#define ACP_SW_AUDIO_RX_OFFSET_DP0 0x0003108
+#define ACP_SW_AUDIO_RX_OFFSET_DP1 0x000310C
+#define ACP_SW_AUDIO_RX_OFFSET_DP2 0x0003110
+#define ACP_SW_AUDIO_RX_OFFSET_DP3 0x0003114
+#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP0 0x0003118
+#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP1 0x000311C
+#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP2 0x0003120
+#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP3 0x0003124
+#define ACP_SW_BT_RX_EN 0x0003128
+#define ACP_SW_BT_RX_EN_STATUS 0x000312C
+#define ACP_SW_BT_RX_FRAME_FORMAT 0x0003130
+#define ACP_SW_BT_RX_SAMPLEINTERVAL 0x0003134
+#define ACP_SW_BT_RX_HCTRL 0x0003138
+#define ACP_SW_BT_RX_OFFSET 0x000313C
+#define ACP_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003140
+#define ACP_SW_HEADSET_RX_EN 0x0003144
+#define ACP_SW_HEADSET_RX_EN_STATUS 0x0003148
+#define ACP_SW_HEADSET_RX_FRAME_FORMAT 0x000314C
+#define ACP_SW_HEADSET_RX_SAMPLEINTERVAL 0x0003150
+#define ACP_SW_HEADSET_RX_HCTRL 0x0003154
+#define ACP_SW_HEADSET_RX_OFFSET 0x0003158
+#define ACP_SW_HEADSET_RX_CHANNEL_ENABLE_DP0 0x000315C
+#define ACP_SW_BPT_PORT_EN 0x0003160
+#define ACP_SW_BPT_PORT_EN_STATUS 0x0003164
+#define ACP_SW_BPT_PORT_FRAME_FORMAT 0x0003168
+#define ACP_SW_BPT_PORT_SAMPLEINTERVAL 0x000316C
+#define ACP_SW_BPT_PORT_HCTRL 0x0003170
+#define ACP_SW_BPT_PORT_OFFSET 0x0003174
+#define ACP_SW_BPT_PORT_CHANNEL_ENABLE 0x0003178
+#define ACP_SW_BPT_PORT_FIRST_BYTE_ADDR 0x000317C
+#define ACP_SW_CLK_RESUME_CTRL 0x0003180
+#define ACP_SW_CLK_RESUME_DELAY_CNTR 0x0003184
+#define ACP_SW_BUS_RESET_CTRL 0x0003188
+#define ACP_SW_PRBS_ERR_STATUS 0x000318C
+#define SW_IMM_CMD_UPPER_WORD 0x0003230
+#define SW_IMM_CMD_LOWER_QWORD 0x0003234
+#define SW_IMM_RESP_UPPER_WORD 0x0003238
+#define SW_IMM_RESP_LOWER_QWORD 0x000323C
+#define SW_IMM_CMD_STS 0x0003240
+#define SW_BRA_BASE_ADDRESS 0x0003244
+#define SW_BRA_TRANSFER_SIZE 0x0003248
+#define SW_BRA_DMA_BUSY 0x000324C
+#define SW_BRA_RESP 0x0003250
+#define SW_BRA_RESP_FRAME_ADDR 0x0003254
+#define SW_BRA_CURRENT_TRANSFER_SIZE 0x0003258
+#define SW_STATE_CHANGE_STATUS_0TO7 0x000325C
+#define SW_STATE_CHANGE_STATUS_8TO11 0x0003260
+#define SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003264
+#define SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003268
+#define SW_CLK_FREQUENCY_CTRL 0x000326C
+#define SW_ERROR_INTR_MASK 0x0003270
+#define SW_PHY_TEST_MODE_DATA_OFF 0x0003274
+
+/* Registers from ACP_P1_AUDIO_BUFFERS block */
+#define ACP_P1_I2S_RX_RINGBUFADDR 0x0003A00
+#define ACP_P1_I2S_RX_RINGBUFSIZE 0x0003A04
+#define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x0003A08
+#define ACP_P1_I2S_RX_FIFOADDR 0x0003A0C
+#define ACP_P1_I2S_RX_FIFOSIZE 0x0003A10
+#define ACP_P1_I2S_RX_DMA_SIZE 0x0003A14
+#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18
+#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C
+#define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x0003A20
+#define ACP_P1_I2S_TX_RINGBUFADDR 0x0003A24
+#define ACP_P1_I2S_TX_RINGBUFSIZE 0x0003A28
+#define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x0003A2C
+#define ACP_P1_I2S_TX_FIFOADDR 0x0003A30
+#define ACP_P1_I2S_TX_FIFOSIZE 0x0003A34
+#define ACP_P1_I2S_TX_DMA_SIZE 0x0003A38
+#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C
+#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0003A40
+#define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x0003A44
+#define ACP_P1_BT_RX_RINGBUFADDR 0x0003A48
+#define ACP_P1_BT_RX_RINGBUFSIZE 0x0003A4C
+#define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x0003A50
+#define ACP_P1_BT_RX_FIFOADDR 0x0003A54
+#define ACP_P1_BT_RX_FIFOSIZE 0x0003A58
+#define ACP_P1_BT_RX_DMA_SIZE 0x0003A5C
+#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60
+#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x0003A64
+#define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x0003A68
+#define ACP_P1_BT_TX_RINGBUFADDR 0x0003A6C
+#define ACP_P1_BT_TX_RINGBUFSIZE 0x0003A70
+#define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x0003A74
+#define ACP_P1_BT_TX_FIFOADDR 0x0003A78
+#define ACP_P1_BT_TX_FIFOSIZE 0x0003A7C
+#define ACP_P1_BT_TX_DMA_SIZE 0x0003A80
+#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84
+#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x0003A88
+#define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x0003A8C
+#define ACP_P1_HS_RX_RINGBUFADDR 0x0003A90
+#define ACP_P1_HS_RX_RINGBUFSIZE 0x0003A94
+#define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x0003A98
+#define ACP_P1_HS_RX_FIFOADDR 0x0003A9C
+#define ACP_P1_HS_RX_FIFOSIZE 0x0003AA0
+#define ACP_P1_HS_RX_DMA_SIZE 0x0003AA4
+#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8
+#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC
+#define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x0003AB0
+#define ACP_P1_HS_TX_RINGBUFADDR 0x0003AB4
+#define ACP_P1_HS_TX_RINGBUFSIZE 0x0003AB8
+#define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x0003ABC
+#define ACP_P1_HS_TX_FIFOADDR 0x0003AC0
+#define ACP_P1_HS_TX_FIFOSIZE 0x0003AC4
+#define ACP_P1_HS_TX_DMA_SIZE 0x0003AC8
+#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC
+#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0
+#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x0003AD4
+#define ACP_P1_AUDIO_RX_RINGBUFADDR ACP_P1_I2S_RX_RINGBUFADDR
+#define ACP_P1_AUDIO_RX_RINGBUFSIZE ACP_P1_I2S_RX_RINGBUFSIZE
+#define ACP_P1_AUDIO_RX_LINKPOSITIONCNTR ACP_P1_I2S_RX_LINKPOSITIONCNTR
+#define ACP_P1_AUDIO_RX_FIFOADDR ACP_P1_I2S_RX_FIFOADDR
+#define ACP_P1_AUDIO_RX_FIFOSIZE ACP_P1_I2S_RX_FIFOSIZE
+#define ACP_P1_AUDIO_RX_DMA_SIZE ACP_P1_I2S_RX_DMA_SIZE
+#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH
+#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW
+#define ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE ACP_P1_I2S_RX_INTR_WATERMARK_SIZE
+#define ACP_P1_AUDIO_TX_RINGBUFADDR ACP_P1_I2S_TX_RINGBUFADDR
+#define ACP_P1_AUDIO_TX_RINGBUFSIZE ACP_P1_I2S_TX_RINGBUFSIZE
+#define ACP_P1_AUDIO_TX_LINKPOSITIONCNTR ACP_P1_I2S_TX_LINKPOSITIONCNTR
+#define ACP_P1_AUDIO_TX_FIFOADDR ACP_P1_I2S_TX_FIFOADDR
+#define ACP_P1_AUDIO_TX_FIFOSIZE ACP_P1_I2S_TX_FIFOSIZE
+#define ACP_P1_AUDIO_TX_DMA_SIZE ACP_P1_I2S_TX_DMA_SIZE
+#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH
+#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW
+#define ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE ACP_P1_I2S_TX_INTR_WATERMARK_SIZE
+
+/* Registers from ACP_P1_SW_SWCLK block */
+#define ACP_P1_SW_EN 0x0003C00
+#define ACP_P1_SW_EN_STATUS 0x0003C04
+#define ACP_P1_SW_FRAMESIZE 0x0003C08
+#define ACP_P1_SW_SSP_COUNTER 0x0003C0C
+#define ACP_P1_SW_BT_TX_EN 0x0003C50
+#define ACP_P1_SW_BT_TX_EN_STATUS 0x0003C54
+#define ACP_P1_SW_BT_TX_FRAME_FORMAT 0x0003C58
+#define ACP_P1_SW_BT_TX_SAMPLEINTERVAL 0x0003C5C
+#define ACP_P1_SW_BT_TX_HCTRL 0x0003C60
+#define ACP_P1_SW_BT_TX_OFFSET 0x0003C64
+#define ACP_P1_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003C68
+#define ACP_P1_SW_BT_RX_EN 0x0003D28
+#define ACP_P1_SW_BT_RX_EN_STATUS 0x0003D2C
+#define ACP_P1_SW_BT_RX_FRAME_FORMAT 0x0003D30
+#define ACP_P1_SW_BT_RX_SAMPLEINTERVAL 0x0003D34
+#define ACP_P1_SW_BT_RX_HCTRL 0x0003D38
+#define ACP_P1_SW_BT_RX_OFFSET 0x0003D3C
+#define ACP_P1_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003D40
+#define ACP_P1_SW_BPT_PORT_EN 0x0003D60
+#define ACP_P1_SW_BPT_PORT_EN_STATUS 0x0003D64
+#define ACP_P1_SW_BPT_PORT_FRAME_FORMAT 0x0003D68
+#define ACP_P1_SW_BPT_PORT_SAMPLEINTERVAL 0x0003D6C
+#define ACP_P1_SW_BPT_PORT_HCTRL 0x0003D70
+#define ACP_P1_SW_BPT_PORT_OFFSET 0x0003D74
+#define ACP_P1_SW_BPT_PORT_CHANNEL_ENABLE 0x0003D78
+#define ACP_P1_SW_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C
+#define ACP_P1_SW_CLK_RESUME_CTRL 0x0003D80
+#define ACP_P1_SW_CLK_RESUME_DELAY_CNTR 0x0003D84
+#define ACP_P1_SW_BUS_RESET_CTRL 0x0003D88
+#define ACP_P1_SW_PRBS_ERR_STATUS 0x0003D8C
+
+/* Registers from ACP_P1_SW_ACLK block */
+#define P1_SW_CORB_BASE_ADDRESS 0x0003E00
+#define P1_SW_CORB_WRITE_POINTER 0x0003E04
+#define P1_SW_CORB_READ_POINTER 0x0003E08
+#define P1_SW_CORB_CONTROL 0x0003E0C
+#define P1_SW_CORB_SIZE 0x0003E14
+#define P1_SW_RIRB_BASE_ADDRESS 0x0003E18
+#define P1_SW_RIRB_WRITE_POINTER 0x0003E1C
+#define P1_SW_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20
+#define P1_SW_RIRB_CONTROL 0x0003E24
+#define P1_SW_RIRB_SIZE 0x0003E28
+#define P1_SW_RIRB_FIFO_MIN_THDL 0x0003E2C
+#define P1_SW_IMM_CMD_UPPER_WORD 0x0003E30
+#define P1_SW_IMM_CMD_LOWER_QWORD 0x0003E34
+#define P1_SW_IMM_RESP_UPPER_WORD 0x0003E38
+#define P1_SW_IMM_RESP_LOWER_QWORD 0x0003E3C
+#define P1_SW_IMM_CMD_STS 0x0003E40
+#define P1_SW_BRA_BASE_ADDRESS 0x0003E44
+#define P1_SW_BRA_TRANSFER_SIZE 0x0003E48
+#define P1_SW_BRA_DMA_BUSY 0x0003E4C
+#define P1_SW_BRA_RESP 0x0003E50
+#define P1_SW_BRA_RESP_FRAME_ADDR 0x0003E54
+#define P1_SW_BRA_CURRENT_TRANSFER_SIZE 0x0003E58
+#define P1_SW_STATE_CHANGE_STATUS_0TO7 0x0003E5C
+#define P1_SW_STATE_CHANGE_STATUS_8TO11 0x0003E60
+#define P1_SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003E64
+#define P1_SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003E68
+#define P1_SW_CLK_FREQUENCY_CTRL 0x0003E6C
+#define P1_SW_ERROR_INTR_MASK 0x0003E70
+#define P1_SW_PHY_TEST_MODE_DATA_OFF 0x0003E74
+
+/* Registers from ACP_SCRATCH block */
+#define ACP_SCRATCH_REG_0 0x0010000
+#define ACP_SCRATCH_REG_1 0x0010004
+#define ACP_SCRATCH_REG_2 0x0010008
+#define ACP_SCRATCH_REG_3 0x001000C
+#define ACP_SCRATCH_REG_4 0x0010010
+#define ACP_SCRATCH_REG_5 0x0010014
+#define ACP_SCRATCH_REG_6 0x0010018
+#define ACP_SCRATCH_REG_7 0x001001C
+#define ACP_SCRATCH_REG_8 0x0010020
+#define ACP_SCRATCH_REG_9 0x0010024
+#define ACP_SCRATCH_REG_10 0x0010028
+#define ACP_SCRATCH_REG_11 0x001002C
+#define ACP_SCRATCH_REG_12 0x0010030
+#define ACP_SCRATCH_REG_13 0x0010034
+#define ACP_SCRATCH_REG_14 0x0010038
+#define ACP_SCRATCH_REG_15 0x001003C
+#define ACP_SCRATCH_REG_16 0x0010040
+#define ACP_SCRATCH_REG_17 0x0010044
+#define ACP_SCRATCH_REG_18 0x0010048
+#define ACP_SCRATCH_REG_19 0x001004C
+#define ACP_SCRATCH_REG_20 0x0010050
+#define ACP_SCRATCH_REG_21 0x0010054
+#define ACP_SCRATCH_REG_22 0x0010058
+#define ACP_SCRATCH_REG_23 0x001005C
+#define ACP_SCRATCH_REG_24 0x0010060
+#define ACP_SCRATCH_REG_25 0x0010064
+#define ACP_SCRATCH_REG_26 0x0010068
+#define ACP_SCRATCH_REG_27 0x001006C
+#define ACP_SCRATCH_REG_28 0x0010070
+#define ACP_SCRATCH_REG_29 0x0010074
+#define ACP_SCRATCH_REG_30 0x0010078
+#define ACP_SCRATCH_REG_31 0x001007C
+#define ACP_SCRATCH_REG_32 0x0010080
+#define ACP_SCRATCH_REG_33 0x0010084
+#define ACP_SCRATCH_REG_34 0x0010088
+#define ACP_SCRATCH_REG_35 0x001008C
+#define ACP_SCRATCH_REG_36 0x0010090
+#define ACP_SCRATCH_REG_37 0x0010094
+#define ACP_SCRATCH_REG_38 0x0010098
+#define ACP_SCRATCH_REG_39 0x001009C
+#define ACP_SCRATCH_REG_40 0x00100A0
+#define ACP_SCRATCH_REG_41 0x00100A4
+#define ACP_SCRATCH_REG_42 0x00100A8
+#define ACP_SCRATCH_REG_43 0x00100AC
+#define ACP_SCRATCH_REG_44 0x00100B0
+#define ACP_SCRATCH_REG_45 0x00100B4
+#define ACP_SCRATCH_REG_46 0x00100B8
+#define ACP_SCRATCH_REG_47 0x00100BC
+#define ACP_SCRATCH_REG_48 0x00100C0
+#define ACP_SCRATCH_REG_49 0x00100C4
+#define ACP_SCRATCH_REG_50 0x00100C8
+#define ACP_SCRATCH_REG_51 0x00100CC
+#define ACP_SCRATCH_REG_52 0x00100D0
+#define ACP_SCRATCH_REG_53 0x00100D4
+#define ACP_SCRATCH_REG_54 0x00100D8
+#define ACP_SCRATCH_REG_55 0x00100DC
+#define ACP_SCRATCH_REG_56 0x00100E0
+#define ACP_SCRATCH_REG_57 0x00100E4
+#define ACP_SCRATCH_REG_58 0x00100E8
+#define ACP_SCRATCH_REG_59 0x00100EC
+#define ACP_SCRATCH_REG_60 0x00100F0
+#define ACP_SCRATCH_REG_61 0x00100F4
+#define ACP_SCRATCH_REG_62 0x00100F8
+#define ACP_SCRATCH_REG_63 0x00100FC
+#define ACP_SCRATCH_REG_64 0x0010100
+#define ACP_SCRATCH_REG_65 0x0010104
+#define ACP_SCRATCH_REG_66 0x0010108
+#define ACP_SCRATCH_REG_67 0x001010C
+#define ACP_SCRATCH_REG_68 0x0010110
+#define ACP_SCRATCH_REG_69 0x0010114
+#define ACP_SCRATCH_REG_70 0x0010118
+#define ACP_SCRATCH_REG_71 0x001011C
+#define ACP_SCRATCH_REG_72 0x0010120
+#define ACP_SCRATCH_REG_73 0x0010124
+#define ACP_SCRATCH_REG_74 0x0010128
+#define ACP_SCRATCH_REG_75 0x001012C
+#define ACP_SCRATCH_REG_76 0x0010130
+#define ACP_SCRATCH_REG_77 0x0010134
+#define ACP_SCRATCH_REG_78 0x0010138
+#define ACP_SCRATCH_REG_79 0x001013C
+#define ACP_SCRATCH_REG_80 0x0010140
+#define ACP_SCRATCH_REG_81 0x0010144
+#define ACP_SCRATCH_REG_82 0x0010148
+#define ACP_SCRATCH_REG_83 0x001014C
+#define ACP_SCRATCH_REG_84 0x0010150
+#define ACP_SCRATCH_REG_85 0x0010154
+#define ACP_SCRATCH_REG_86 0x0010158
+#define ACP_SCRATCH_REG_87 0x001015C
+#define ACP_SCRATCH_REG_88 0x0010160
+#define ACP_SCRATCH_REG_89 0x0010164
+#define ACP_SCRATCH_REG_90 0x0010168
+#define ACP_SCRATCH_REG_91 0x001016C
+#define ACP_SCRATCH_REG_92 0x0010170
+#define ACP_SCRATCH_REG_93 0x0010174
+#define ACP_SCRATCH_REG_94 0x0010178
+#define ACP_SCRATCH_REG_95 0x001017C
+#define ACP_SCRATCH_REG_96 0x0010180
+#define ACP_SCRATCH_REG_97 0x0010184
+#define ACP_SCRATCH_REG_98 0x0010188
+#define ACP_SCRATCH_REG_99 0x001018C
+#define ACP_SCRATCH_REG_100 0x0010190
+#define ACP_SCRATCH_REG_101 0x0010194
+#define ACP_SCRATCH_REG_102 0x0010198
+#define ACP_SCRATCH_REG_103 0x001019C
+#define ACP_SCRATCH_REG_104 0x00101A0
+#define ACP_SCRATCH_REG_105 0x00101A4
+#define ACP_SCRATCH_REG_106 0x00101A8
+#define ACP_SCRATCH_REG_107 0x00101AC
+#define ACP_SCRATCH_REG_108 0x00101B0
+#define ACP_SCRATCH_REG_109 0x00101B4
+#define ACP_SCRATCH_REG_110 0x00101B8
+#define ACP_SCRATCH_REG_111 0x00101BC
+#define ACP_SCRATCH_REG_112 0x00101C0
+#define ACP_SCRATCH_REG_113 0x00101C4
+#define ACP_SCRATCH_REG_114 0x00101C8
+#define ACP_SCRATCH_REG_115 0x00101CC
+#define ACP_SCRATCH_REG_116 0x00101D0
+#define ACP_SCRATCH_REG_117 0x00101D4
+#define ACP_SCRATCH_REG_118 0x00101D8
+#define ACP_SCRATCH_REG_119 0x00101DC
+#define ACP_SCRATCH_REG_120 0x00101E0
+#define ACP_SCRATCH_REG_121 0x00101E4
+#define ACP_SCRATCH_REG_122 0x00101E8
+#define ACP_SCRATCH_REG_123 0x00101EC
+#define ACP_SCRATCH_REG_124 0x00101F0
+#define ACP_SCRATCH_REG_125 0x00101F4
+#define ACP_SCRATCH_REG_126 0x00101F8
+#define ACP_SCRATCH_REG_127 0x00101FC
+#define ACP_SCRATCH_REG_128 0x0010200
+#endif
If unsure select "N".
config SND_SOC_AMD_PS
- tristate "AMD Audio Coprocessor-v6.2 Pink Sardine support"
+ tristate "AMD Audio Coprocessor-v6.3 Pink Sardine support"
depends on X86 && PCI && ACPI
help
- This option enables Audio Coprocessor i.e ACP v6.2 support on
+ This option enables Audio Coprocessor i.e ACP v6.3 support on
AMD Pink sardine platform. By enabling this flag build will be
triggered for ACP PCI driver, ACP PDM DMA driver.
Say m if you have such a device.
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * AMD ALSA SoC PDM Driver
- *
- * Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.
- */
-
-#include <sound/acp62_chip_offset_byte.h>
-
-#define ACP_DEVICE_ID 0x15E2
-#define ACP6x_REG_START 0x1240000
-#define ACP6x_REG_END 0x1250200
-#define ACP6x_DEVS 3
-#define ACP6x_PDM_MODE 1
-
-#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
-#define ACP_PGFSM_CNTL_POWER_ON_MASK 1
-#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
-#define ACP_PGFSM_STATUS_MASK 3
-#define ACP_POWERED_ON 0
-#define ACP_POWER_ON_IN_PROGRESS 1
-#define ACP_POWERED_OFF 2
-#define ACP_POWER_OFF_IN_PROGRESS 3
-
-#define ACP_ERROR_MASK 0x20000000
-#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
-#define PDM_DMA_STAT 0x10
-
-#define PDM_DMA_INTR_MASK 0x10000
-#define ACP_ERROR_STAT 29
-#define PDM_DECIMATION_FACTOR 2
-#define ACP_PDM_CLK_FREQ_MASK 7
-#define ACP_WOV_MISC_CTRL_MASK 0x10
-#define ACP_PDM_ENABLE 1
-#define ACP_PDM_DISABLE 0
-#define ACP_PDM_DMA_EN_STATUS 2
-#define TWO_CH 2
-#define DELAY_US 5
-#define ACP_COUNTER 20000
-
-#define ACP_SRAM_PTE_OFFSET 0x03800000
-#define PAGE_SIZE_4K_ENABLE 2
-#define PDM_PTE_OFFSET 0
-#define PDM_MEM_WINDOW_START 0x4000000
-
-#define CAPTURE_MIN_NUM_PERIODS 4
-#define CAPTURE_MAX_NUM_PERIODS 4
-#define CAPTURE_MAX_PERIOD_SIZE 8192
-#define CAPTURE_MIN_PERIOD_SIZE 4096
-
-#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
-#define MIN_BUFFER MAX_BUFFER
-
-/* time in ms for runtime suspend delay */
-#define ACP_SUSPEND_DELAY_MS 2000
-
-enum acp_config {
- ACP_CONFIG_0 = 0,
- ACP_CONFIG_1,
- ACP_CONFIG_2,
- ACP_CONFIG_3,
- ACP_CONFIG_4,
- ACP_CONFIG_5,
- ACP_CONFIG_6,
- ACP_CONFIG_7,
- ACP_CONFIG_8,
- ACP_CONFIG_9,
- ACP_CONFIG_10,
- ACP_CONFIG_11,
- ACP_CONFIG_12,
- ACP_CONFIG_13,
- ACP_CONFIG_14,
- ACP_CONFIG_15,
-};
-
-struct pdm_stream_instance {
- u16 num_pages;
- u16 channels;
- dma_addr_t dma_addr;
- u64 bytescount;
- void __iomem *acp62_base;
-};
-
-struct pdm_dev_data {
- u32 pdm_irq;
- void __iomem *acp62_base;
- struct snd_pcm_substream *capture_stream;
-};
-
-static inline u32 acp62_readl(void __iomem *base_addr)
-{
- return readl(base_addr);
-}
-
-static inline void acp62_writel(u32 val, void __iomem *base_addr)
-{
- writel(val, base_addr);
-}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * AMD ALSA SoC PDM Driver
+ *
+ * Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.
+ */
+
+#include <sound/acp63_chip_offset_byte.h>
+
+#define ACP_DEVICE_ID 0x15E2
+#define ACP6x_REG_START 0x1240000
+#define ACP6x_REG_END 0x1250200
+#define ACP6x_DEVS 3
+#define ACP6x_PDM_MODE 1
+
+#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
+#define ACP_PGFSM_CNTL_POWER_ON_MASK 1
+#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
+#define ACP_PGFSM_STATUS_MASK 3
+#define ACP_POWERED_ON 0
+#define ACP_POWER_ON_IN_PROGRESS 1
+#define ACP_POWERED_OFF 2
+#define ACP_POWER_OFF_IN_PROGRESS 3
+
+#define ACP_ERROR_MASK 0x20000000
+#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
+#define PDM_DMA_STAT 0x10
+
+#define PDM_DMA_INTR_MASK 0x10000
+#define ACP_ERROR_STAT 29
+#define PDM_DECIMATION_FACTOR 2
+#define ACP_PDM_CLK_FREQ_MASK 7
+#define ACP_WOV_MISC_CTRL_MASK 0x10
+#define ACP_PDM_ENABLE 1
+#define ACP_PDM_DISABLE 0
+#define ACP_PDM_DMA_EN_STATUS 2
+#define TWO_CH 2
+#define DELAY_US 5
+#define ACP_COUNTER 20000
+
+#define ACP_SRAM_PTE_OFFSET 0x03800000
+#define PAGE_SIZE_4K_ENABLE 2
+#define PDM_PTE_OFFSET 0
+#define PDM_MEM_WINDOW_START 0x4000000
+
+#define CAPTURE_MIN_NUM_PERIODS 4
+#define CAPTURE_MAX_NUM_PERIODS 4
+#define CAPTURE_MAX_PERIOD_SIZE 8192
+#define CAPTURE_MIN_PERIOD_SIZE 4096
+
+#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
+#define MIN_BUFFER MAX_BUFFER
+
+/* time in ms for runtime suspend delay */
+#define ACP_SUSPEND_DELAY_MS 2000
+
+enum acp_config {
+ ACP_CONFIG_0 = 0,
+ ACP_CONFIG_1,
+ ACP_CONFIG_2,
+ ACP_CONFIG_3,
+ ACP_CONFIG_4,
+ ACP_CONFIG_5,
+ ACP_CONFIG_6,
+ ACP_CONFIG_7,
+ ACP_CONFIG_8,
+ ACP_CONFIG_9,
+ ACP_CONFIG_10,
+ ACP_CONFIG_11,
+ ACP_CONFIG_12,
+ ACP_CONFIG_13,
+ ACP_CONFIG_14,
+ ACP_CONFIG_15,
+};
+
+struct pdm_stream_instance {
+ u16 num_pages;
+ u16 channels;
+ dma_addr_t dma_addr;
+ u64 bytescount;
+ void __iomem *acp63_base;
+};
+
+struct pdm_dev_data {
+ u32 pdm_irq;
+ void __iomem *acp63_base;
+ struct snd_pcm_substream *capture_stream;
+};
+
+static inline u32 acp63_readl(void __iomem *base_addr)
+{
+ return readl(base_addr);
+}
+
+static inline void acp63_writel(u32 val, void __iomem *base_addr)
+{
+ writel(val, base_addr);
+}
#include <sound/pcm_params.h>
#include <linux/pm_runtime.h>
-#include "acp62.h"
+#include "acp63.h"
-struct acp62_dev_data {
- void __iomem *acp62_base;
+struct acp63_dev_data {
+ void __iomem *acp63_base;
struct resource *res;
- bool acp62_audio_mode;
+ bool acp63_audio_mode;
struct platform_device *pdev[ACP6x_DEVS];
};
-static int acp62_power_on(void __iomem *acp_base)
+static int acp63_power_on(void __iomem *acp_base)
{
u32 val;
int timeout;
- val = acp62_readl(acp_base + ACP_PGFSM_STATUS);
+ val = acp63_readl(acp_base + ACP_PGFSM_STATUS);
if (!val)
return val;
if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)
- acp62_writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
+ acp63_writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
timeout = 0;
while (++timeout < 500) {
- val = acp62_readl(acp_base + ACP_PGFSM_STATUS);
+ val = acp63_readl(acp_base + ACP_PGFSM_STATUS);
if (!val)
return 0;
udelay(1);
return -ETIMEDOUT;
}
-static int acp62_reset(void __iomem *acp_base)
+static int acp63_reset(void __iomem *acp_base)
{
u32 val;
int timeout;
- acp62_writel(1, acp_base + ACP_SOFT_RESET);
+ acp63_writel(1, acp_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
- val = acp62_readl(acp_base + ACP_SOFT_RESET);
+ val = acp63_readl(acp_base + ACP_SOFT_RESET);
if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
break;
cpu_relax();
}
- acp62_writel(0, acp_base + ACP_SOFT_RESET);
+ acp63_writel(0, acp_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
- val = acp62_readl(acp_base + ACP_SOFT_RESET);
+ val = acp63_readl(acp_base + ACP_SOFT_RESET);
if (!val)
return 0;
cpu_relax();
return -ETIMEDOUT;
}
-static void acp62_enable_interrupts(void __iomem *acp_base)
+static void acp63_enable_interrupts(void __iomem *acp_base)
{
- acp62_writel(1, acp_base + ACP_EXTERNAL_INTR_ENB);
+ acp63_writel(1, acp_base + ACP_EXTERNAL_INTR_ENB);
}
-static void acp62_disable_interrupts(void __iomem *acp_base)
+static void acp63_disable_interrupts(void __iomem *acp_base)
{
- acp62_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base +
+ acp63_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base +
ACP_EXTERNAL_INTR_STAT);
- acp62_writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL);
- acp62_writel(0, acp_base + ACP_EXTERNAL_INTR_ENB);
+ acp63_writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL);
+ acp63_writel(0, acp_base + ACP_EXTERNAL_INTR_ENB);
}
-static int acp62_init(void __iomem *acp_base, struct device *dev)
+static int acp63_init(void __iomem *acp_base, struct device *dev)
{
int ret;
- ret = acp62_power_on(acp_base);
+ ret = acp63_power_on(acp_base);
if (ret) {
dev_err(dev, "ACP power on failed\n");
return ret;
}
- acp62_writel(0x01, acp_base + ACP_CONTROL);
- ret = acp62_reset(acp_base);
+ acp63_writel(0x01, acp_base + ACP_CONTROL);
+ ret = acp63_reset(acp_base);
if (ret) {
dev_err(dev, "ACP reset failed\n");
return ret;
}
- acp62_writel(0x03, acp_base + ACP_CLKMUX_SEL);
- acp62_enable_interrupts(acp_base);
+ acp63_writel(0x03, acp_base + ACP_CLKMUX_SEL);
+ acp63_enable_interrupts(acp_base);
return 0;
}
-static int acp62_deinit(void __iomem *acp_base, struct device *dev)
+static int acp63_deinit(void __iomem *acp_base, struct device *dev)
{
int ret;
- acp62_disable_interrupts(acp_base);
- ret = acp62_reset(acp_base);
+ acp63_disable_interrupts(acp_base);
+ ret = acp63_reset(acp_base);
if (ret) {
dev_err(dev, "ACP reset failed\n");
return ret;
}
- acp62_writel(0, acp_base + ACP_CLKMUX_SEL);
- acp62_writel(0, acp_base + ACP_CONTROL);
+ acp63_writel(0, acp_base + ACP_CLKMUX_SEL);
+ acp63_writel(0, acp_base + ACP_CONTROL);
return 0;
}
-static irqreturn_t acp62_irq_handler(int irq, void *dev_id)
+static irqreturn_t acp63_irq_handler(int irq, void *dev_id)
{
- struct acp62_dev_data *adata;
+ struct acp63_dev_data *adata;
struct pdm_dev_data *ps_pdm_data;
u32 val;
if (!adata)
return IRQ_NONE;
- val = acp62_readl(adata->acp62_base + ACP_EXTERNAL_INTR_STAT);
+ val = acp63_readl(adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
if (val & BIT(PDM_DMA_STAT)) {
ps_pdm_data = dev_get_drvdata(&adata->pdev[0]->dev);
- acp62_writel(BIT(PDM_DMA_STAT), adata->acp62_base + ACP_EXTERNAL_INTR_STAT);
+ acp63_writel(BIT(PDM_DMA_STAT), adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
if (ps_pdm_data->capture_stream)
snd_pcm_period_elapsed(ps_pdm_data->capture_stream);
return IRQ_HANDLED;
return IRQ_NONE;
}
-static int snd_acp62_probe(struct pci_dev *pci,
+static int snd_acp63_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
- struct acp62_dev_data *adata;
+ struct acp63_dev_data *adata;
struct platform_device_info pdevinfo[ACP6x_DEVS];
int index, ret;
int val = 0x00;
case 0x63:
break;
default:
- dev_dbg(&pci->dev, "acp62 pci device not found\n");
+ dev_dbg(&pci->dev, "acp63 pci device not found\n");
return -ENODEV;
}
if (pci_enable_device(pci)) {
dev_err(&pci->dev, "pci_request_regions failed\n");
goto disable_pci;
}
- adata = devm_kzalloc(&pci->dev, sizeof(struct acp62_dev_data),
+ adata = devm_kzalloc(&pci->dev, sizeof(struct acp63_dev_data),
GFP_KERNEL);
if (!adata) {
ret = -ENOMEM;
}
addr = pci_resource_start(pci, 0);
- adata->acp62_base = devm_ioremap(&pci->dev, addr,
+ adata->acp63_base = devm_ioremap(&pci->dev, addr,
pci_resource_len(pci, 0));
- if (!adata->acp62_base) {
+ if (!adata->acp63_base) {
ret = -ENOMEM;
goto release_regions;
}
pci_set_master(pci);
pci_set_drvdata(pci, adata);
- ret = acp62_init(adata->acp62_base, &pci->dev);
+ ret = acp63_init(adata->acp63_base, &pci->dev);
if (ret)
goto release_regions;
- val = acp62_readl(adata->acp62_base + ACP_PIN_CONFIG);
+ val = acp63_readl(adata->acp63_base + ACP_PIN_CONFIG);
switch (val) {
case ACP_CONFIG_0:
case ACP_CONFIG_1:
adata->res->flags = IORESOURCE_MEM;
adata->res->start = addr;
adata->res->end = addr + (ACP6x_REG_END - ACP6x_REG_START);
- adata->acp62_audio_mode = ACP6x_PDM_MODE;
+ adata->acp63_audio_mode = ACP6x_PDM_MODE;
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo[0].name = "acp_ps_pdm_dma";
ret = PTR_ERR(adata->pdev[index]);
goto unregister_devs;
}
- ret = devm_request_irq(&pci->dev, pci->irq, acp62_irq_handler,
+ ret = devm_request_irq(&pci->dev, pci->irq, acp63_irq_handler,
irqflags, "ACP_PCI_IRQ", adata);
if (ret) {
dev_err(&pci->dev, "ACP PCI IRQ request failed\n");
for (--index; index >= 0; index--)
platform_device_unregister(adata->pdev[index]);
de_init:
- if (acp62_deinit(adata->acp62_base, &pci->dev))
+ if (acp63_deinit(adata->acp63_base, &pci->dev))
dev_err(&pci->dev, "ACP de-init failed\n");
release_regions:
pci_release_regions(pci);
return ret;
}
-static int __maybe_unused snd_acp62_suspend(struct device *dev)
+static int __maybe_unused snd_acp63_suspend(struct device *dev)
{
- struct acp62_dev_data *adata;
+ struct acp63_dev_data *adata;
int ret;
adata = dev_get_drvdata(dev);
- ret = acp62_deinit(adata->acp62_base, dev);
+ ret = acp63_deinit(adata->acp63_base, dev);
if (ret)
dev_err(dev, "ACP de-init failed\n");
return ret;
}
-static int __maybe_unused snd_acp62_resume(struct device *dev)
+static int __maybe_unused snd_acp63_resume(struct device *dev)
{
- struct acp62_dev_data *adata;
+ struct acp63_dev_data *adata;
int ret;
adata = dev_get_drvdata(dev);
- ret = acp62_init(adata->acp62_base, dev);
+ ret = acp63_init(adata->acp63_base, dev);
if (ret)
dev_err(dev, "ACP init failed\n");
return ret;
}
-static const struct dev_pm_ops acp62_pm_ops = {
- SET_RUNTIME_PM_OPS(snd_acp62_suspend, snd_acp62_resume, NULL)
- SET_SYSTEM_SLEEP_PM_OPS(snd_acp62_suspend, snd_acp62_resume)
+static const struct dev_pm_ops acp63_pm_ops = {
+ SET_RUNTIME_PM_OPS(snd_acp63_suspend, snd_acp63_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(snd_acp63_suspend, snd_acp63_resume)
};
-static void snd_acp62_remove(struct pci_dev *pci)
+static void snd_acp63_remove(struct pci_dev *pci)
{
- struct acp62_dev_data *adata;
+ struct acp63_dev_data *adata;
int ret, index;
adata = pci_get_drvdata(pci);
- if (adata->acp62_audio_mode == ACP6x_PDM_MODE) {
+ if (adata->acp63_audio_mode == ACP6x_PDM_MODE) {
for (index = 0; index < ACP6x_DEVS; index++)
platform_device_unregister(adata->pdev[index]);
}
- ret = acp62_deinit(adata->acp62_base, &pci->dev);
+ ret = acp63_deinit(adata->acp63_base, &pci->dev);
if (ret)
dev_err(&pci->dev, "ACP de-init failed\n");
pm_runtime_forbid(&pci->dev);
pci_disable_device(pci);
}
-static const struct pci_device_id snd_acp62_ids[] = {
+static const struct pci_device_id snd_acp63_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
.class_mask = 0xffffff },
{ 0, },
};
-MODULE_DEVICE_TABLE(pci, snd_acp62_ids);
+MODULE_DEVICE_TABLE(pci, snd_acp63_ids);
-static struct pci_driver ps_acp62_driver = {
+static struct pci_driver ps_acp63_driver = {
.name = KBUILD_MODNAME,
- .id_table = snd_acp62_ids,
- .probe = snd_acp62_probe,
- .remove = snd_acp62_remove,
+ .id_table = snd_acp63_ids,
+ .probe = snd_acp63_probe,
+ .remove = snd_acp63_remove,
.driver = {
- .pm = &acp62_pm_ops,
+ .pm = &acp63_pm_ops,
}
};
-module_pci_driver(ps_acp62_driver);
+module_pci_driver(ps_acp63_driver);
MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
MODULE_AUTHOR("Syed.SabaKareem@amd.com");
#include <linux/io.h>
#include <linux/dmi.h>
-#include "acp62.h"
+#include "acp63.h"
#define DRV_NAME "acp_ps_mach"
-SND_SOC_DAILINK_DEF(acp62_pdm,
+SND_SOC_DAILINK_DEF(acp63_pdm,
DAILINK_COMP_ARRAY(COMP_CPU("acp_ps_pdm_dma.0")));
SND_SOC_DAILINK_DEF(dmic_codec,
SND_SOC_DAILINK_DEF(pdm_platform,
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp_ps_pdm_dma.0")));
-static struct snd_soc_dai_link acp62_dai_pdm[] = {
+static struct snd_soc_dai_link acp63_dai_pdm[] = {
{
- .name = "acp62-dmic-capture",
+ .name = "acp63-dmic-capture",
.stream_name = "DMIC capture",
.capture_only = 1,
- SND_SOC_DAILINK_REG(acp62_pdm, dmic_codec, pdm_platform),
+ SND_SOC_DAILINK_REG(acp63_pdm, dmic_codec, pdm_platform),
},
};
-static struct snd_soc_card acp62_card = {
- .name = "acp62",
+static struct snd_soc_card acp63_card = {
+ .name = "acp63",
.owner = THIS_MODULE,
- .dai_link = acp62_dai_pdm,
+ .dai_link = acp63_dai_pdm,
.num_links = 1,
};
-static int acp62_probe(struct platform_device *pdev)
+static int acp63_probe(struct platform_device *pdev)
{
- struct acp62_pdm *machine = NULL;
+ struct acp63_pdm *machine = NULL;
struct snd_soc_card *card;
int ret;
- platform_set_drvdata(pdev, &acp62_card);
+ platform_set_drvdata(pdev, &acp63_card);
card = platform_get_drvdata(pdev);
- acp62_card.dev = &pdev->dev;
+ acp63_card.dev = &pdev->dev;
snd_soc_card_set_drvdata(card, machine);
ret = devm_snd_soc_register_card(&pdev->dev, card);
return 0;
}
-static struct platform_driver acp62_mach_driver = {
+static struct platform_driver acp63_mach_driver = {
.driver = {
.name = "acp_ps_mach",
.pm = &snd_soc_pm_ops,
},
- .probe = acp62_probe,
+ .probe = acp63_probe,
};
-module_platform_driver(acp62_mach_driver);
+module_platform_driver(acp63_mach_driver);
MODULE_AUTHOR("Syed.SabaKareem@amd.com");
MODULE_LICENSE("GPL v2");
#include <sound/soc-dai.h>
#include <linux/pm_runtime.h>
-#include "acp62.h"
+#include "acp63.h"
#define DRV_NAME "acp_ps_pdm_dma"
-static const struct snd_pcm_hardware acp62_pdm_hardware_capture = {
+static const struct snd_pcm_hardware acp63_pdm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
-static void acp62_init_pdm_ring_buffer(u32 physical_addr, u32 buffer_size,
+static void acp63_init_pdm_ring_buffer(u32 physical_addr, u32 buffer_size,
u32 watermark_size, void __iomem *acp_base)
{
- acp62_writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
- acp62_writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
- acp62_writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
- acp62_writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
+ acp63_writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
+ acp63_writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
+ acp63_writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
+ acp63_writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
}
-static void acp62_enable_pdm_clock(void __iomem *acp_base)
+static void acp63_enable_pdm_clock(void __iomem *acp_base)
{
u32 pdm_clk_enable, pdm_ctrl;
pdm_clk_enable = ACP_PDM_CLK_FREQ_MASK;
pdm_ctrl = 0x00;
- acp62_writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
- pdm_ctrl = acp62_readl(acp_base + ACP_WOV_MISC_CTRL);
+ acp63_writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
+ pdm_ctrl = acp63_readl(acp_base + ACP_WOV_MISC_CTRL);
pdm_ctrl |= ACP_WOV_MISC_CTRL_MASK;
- acp62_writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
+ acp63_writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
}
-static void acp62_enable_pdm_interrupts(void __iomem *acp_base)
+static void acp63_enable_pdm_interrupts(void __iomem *acp_base)
{
u32 ext_int_ctrl;
- ext_int_ctrl = acp62_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
+ ext_int_ctrl = acp63_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_int_ctrl |= PDM_DMA_INTR_MASK;
- acp62_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
+ acp63_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
}
-static void acp62_disable_pdm_interrupts(void __iomem *acp_base)
+static void acp63_disable_pdm_interrupts(void __iomem *acp_base)
{
u32 ext_int_ctrl;
- ext_int_ctrl = acp62_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
+ ext_int_ctrl = acp63_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_int_ctrl &= ~PDM_DMA_INTR_MASK;
- acp62_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
+ acp63_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
}
-static bool acp62_check_pdm_dma_status(void __iomem *acp_base)
+static bool acp63_check_pdm_dma_status(void __iomem *acp_base)
{
bool pdm_dma_status;
u32 pdm_enable, pdm_dma_enable;
pdm_dma_status = false;
- pdm_enable = acp62_readl(acp_base + ACP_WOV_PDM_ENABLE);
- pdm_dma_enable = acp62_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
+ pdm_enable = acp63_readl(acp_base + ACP_WOV_PDM_ENABLE);
+ pdm_dma_enable = acp63_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_enable & ACP_PDM_ENABLE) && (pdm_dma_enable & ACP_PDM_DMA_EN_STATUS))
pdm_dma_status = true;
return pdm_dma_status;
}
-static int acp62_start_pdm_dma(void __iomem *acp_base)
+static int acp63_start_pdm_dma(void __iomem *acp_base)
{
u32 pdm_enable;
u32 pdm_dma_enable;
pdm_enable = 0x01;
pdm_dma_enable = 0x01;
- acp62_enable_pdm_clock(acp_base);
- acp62_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
- acp62_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
+ acp63_enable_pdm_clock(acp_base);
+ acp63_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
+ acp63_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
timeout = 0;
while (++timeout < ACP_COUNTER) {
- pdm_dma_enable = acp62_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
+ pdm_dma_enable = acp63_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_dma_enable & 0x02) == ACP_PDM_DMA_EN_STATUS)
return 0;
udelay(DELAY_US);
return -ETIMEDOUT;
}
-static int acp62_stop_pdm_dma(void __iomem *acp_base)
+static int acp63_stop_pdm_dma(void __iomem *acp_base)
{
u32 pdm_enable, pdm_dma_enable;
int timeout;
pdm_enable = 0x00;
pdm_dma_enable = 0x00;
- pdm_enable = acp62_readl(acp_base + ACP_WOV_PDM_ENABLE);
- pdm_dma_enable = acp62_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
+ pdm_enable = acp63_readl(acp_base + ACP_WOV_PDM_ENABLE);
+ pdm_dma_enable = acp63_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if (pdm_dma_enable & 0x01) {
pdm_dma_enable = 0x02;
- acp62_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
+ acp63_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
timeout = 0;
while (++timeout < ACP_COUNTER) {
- pdm_dma_enable = acp62_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
+ pdm_dma_enable = acp63_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_dma_enable & 0x02) == 0x00)
break;
udelay(DELAY_US);
}
if (pdm_enable == ACP_PDM_ENABLE) {
pdm_enable = ACP_PDM_DISABLE;
- acp62_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
+ acp63_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
}
- acp62_writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
+ acp63_writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
return 0;
}
-static void acp62_config_dma(struct pdm_stream_instance *rtd, int direction)
+static void acp63_config_dma(struct pdm_stream_instance *rtd, int direction)
{
u16 page_idx;
u32 low, high, val;
val = PDM_PTE_OFFSET;
/* Group Enable */
- acp62_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp62_base +
+ acp63_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp63_base +
ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
- acp62_writel(PAGE_SIZE_4K_ENABLE, rtd->acp62_base +
+ acp63_writel(PAGE_SIZE_4K_ENABLE, rtd->acp63_base +
ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
low = lower_32_bits(addr);
high = upper_32_bits(addr);
- acp62_writel(low, rtd->acp62_base + ACP_SCRATCH_REG_0 + val);
+ acp63_writel(low, rtd->acp63_base + ACP_SCRATCH_REG_0 + val);
high |= BIT(31);
- acp62_writel(high, rtd->acp62_base + ACP_SCRATCH_REG_0 + val + 4);
+ acp63_writel(high, rtd->acp63_base + ACP_SCRATCH_REG_0 + val + 4);
val += 8;
addr += PAGE_SIZE;
}
}
-static int acp62_pdm_dma_open(struct snd_soc_component *component,
+static int acp63_pdm_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime;
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
- runtime->hw = acp62_pdm_hardware_capture;
+ runtime->hw = acp63_pdm_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
return ret;
}
- acp62_enable_pdm_interrupts(adata->acp62_base);
+ acp63_enable_pdm_interrupts(adata->acp63_base);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
adata->capture_stream = substream;
- pdm_data->acp62_base = adata->acp62_base;
+ pdm_data->acp63_base = adata->acp63_base;
runtime->private_data = pdm_data;
return ret;
}
-static int acp62_pdm_dma_hw_params(struct snd_soc_component *component,
+static int acp63_pdm_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
period_bytes = params_period_bytes(params);
rtd->dma_addr = substream->runtime->dma_addr;
rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
- acp62_config_dma(rtd, substream->stream);
- acp62_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, size,
- period_bytes, rtd->acp62_base);
+ acp63_config_dma(rtd, substream->stream);
+ acp63_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, size,
+ period_bytes, rtd->acp63_base);
return 0;
}
-static u64 acp62_pdm_get_byte_count(struct pdm_stream_instance *rtd,
+static u64 acp63_pdm_get_byte_count(struct pdm_stream_instance *rtd,
int direction)
{
u32 high, low;
u64 byte_count;
- high = acp62_readl(rtd->acp62_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
+ high = acp63_readl(rtd->acp63_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
byte_count = high;
- low = acp62_readl(rtd->acp62_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
+ low = acp63_readl(rtd->acp63_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
byte_count = (byte_count << 32) | low;
return byte_count;
}
-static snd_pcm_uframes_t acp62_pdm_dma_pointer(struct snd_soc_component *comp,
+static snd_pcm_uframes_t acp63_pdm_dma_pointer(struct snd_soc_component *comp,
struct snd_pcm_substream *stream)
{
struct pdm_stream_instance *rtd;
rtd = stream->runtime->private_data;
buffersize = frames_to_bytes(stream->runtime,
stream->runtime->buffer_size);
- bytescount = acp62_pdm_get_byte_count(rtd, stream->stream);
+ bytescount = acp63_pdm_get_byte_count(rtd, stream->stream);
if (bytescount > rtd->bytescount)
bytescount -= rtd->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(stream->runtime, pos);
}
-static int acp62_pdm_dma_new(struct snd_soc_component *component,
+static int acp63_pdm_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *parent = component->dev->parent;
return 0;
}
-static int acp62_pdm_dma_close(struct snd_soc_component *component,
+static int acp63_pdm_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct pdm_dev_data *adata = dev_get_drvdata(component->dev);
struct snd_pcm_runtime *runtime = substream->runtime;
- acp62_disable_pdm_interrupts(adata->acp62_base);
+ acp63_disable_pdm_interrupts(adata->acp63_base);
adata->capture_stream = NULL;
kfree(runtime->private_data);
return 0;
}
-static int acp62_pdm_dai_trigger(struct snd_pcm_substream *substream,
+static int acp63_pdm_dai_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct pdm_stream_instance *rtd;
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
- acp62_writel(ch_mask, rtd->acp62_base + ACP_WOV_PDM_NO_OF_CHANNELS);
- acp62_writel(PDM_DECIMATION_FACTOR, rtd->acp62_base +
+ acp63_writel(ch_mask, rtd->acp63_base + ACP_WOV_PDM_NO_OF_CHANNELS);
+ acp63_writel(PDM_DECIMATION_FACTOR, rtd->acp63_base +
ACP_WOV_PDM_DECIMATION_FACTOR);
- rtd->bytescount = acp62_pdm_get_byte_count(rtd, substream->stream);
- pdm_status = acp62_check_pdm_dma_status(rtd->acp62_base);
+ rtd->bytescount = acp63_pdm_get_byte_count(rtd, substream->stream);
+ pdm_status = acp63_check_pdm_dma_status(rtd->acp63_base);
if (!pdm_status)
- ret = acp62_start_pdm_dma(rtd->acp62_base);
+ ret = acp63_start_pdm_dma(rtd->acp63_base);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
- pdm_status = acp62_check_pdm_dma_status(rtd->acp62_base);
+ pdm_status = acp63_check_pdm_dma_status(rtd->acp63_base);
if (pdm_status)
- ret = acp62_stop_pdm_dma(rtd->acp62_base);
+ ret = acp63_stop_pdm_dma(rtd->acp63_base);
break;
default:
ret = -EINVAL;
return ret;
}
-static const struct snd_soc_dai_ops acp62_pdm_dai_ops = {
- .trigger = acp62_pdm_dai_trigger,
+static const struct snd_soc_dai_ops acp63_pdm_dai_ops = {
+ .trigger = acp63_pdm_dai_trigger,
};
-static struct snd_soc_dai_driver acp62_pdm_dai_driver = {
+static struct snd_soc_dai_driver acp63_pdm_dai_driver = {
.name = "acp_ps_pdm_dma.0",
.capture = {
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
},
- .ops = &acp62_pdm_dai_ops,
+ .ops = &acp63_pdm_dai_ops,
};
-static const struct snd_soc_component_driver acp62_pdm_component = {
+static const struct snd_soc_component_driver acp63_pdm_component = {
.name = DRV_NAME,
- .open = acp62_pdm_dma_open,
- .close = acp62_pdm_dma_close,
- .hw_params = acp62_pdm_dma_hw_params,
- .pointer = acp62_pdm_dma_pointer,
- .pcm_construct = acp62_pdm_dma_new,
+ .open = acp63_pdm_dma_open,
+ .close = acp63_pdm_dma_close,
+ .hw_params = acp63_pdm_dma_hw_params,
+ .pointer = acp63_pdm_dma_pointer,
+ .pcm_construct = acp63_pdm_dma_new,
};
-static int acp62_pdm_audio_probe(struct platform_device *pdev)
+static int acp63_pdm_audio_probe(struct platform_device *pdev)
{
struct resource *res;
struct pdm_dev_data *adata;
if (!adata)
return -ENOMEM;
- adata->acp62_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
- if (!adata->acp62_base)
+ adata->acp63_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!adata->acp63_base)
return -ENOMEM;
adata->capture_stream = NULL;
dev_set_drvdata(&pdev->dev, adata);
status = devm_snd_soc_register_component(&pdev->dev,
- &acp62_pdm_component,
- &acp62_pdm_dai_driver, 1);
+ &acp63_pdm_component,
+ &acp63_pdm_dai_driver, 1);
if (status) {
dev_err(&pdev->dev, "Fail to register acp pdm dai\n");
return 0;
}
-static int acp62_pdm_audio_remove(struct platform_device *pdev)
+static int acp63_pdm_audio_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
return 0;
}
-static int __maybe_unused acp62_pdm_resume(struct device *dev)
+static int __maybe_unused acp63_pdm_resume(struct device *dev)
{
struct pdm_dev_data *adata;
struct snd_pcm_runtime *runtime;
rtd = runtime->private_data;
period_bytes = frames_to_bytes(runtime, runtime->period_size);
buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
- acp62_config_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
- acp62_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, buffer_len,
- period_bytes, adata->acp62_base);
+ acp63_config_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
+ acp63_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, buffer_len,
+ period_bytes, adata->acp63_base);
}
- acp62_enable_pdm_interrupts(adata->acp62_base);
+ acp63_enable_pdm_interrupts(adata->acp63_base);
return 0;
}
-static int __maybe_unused acp62_pdm_suspend(struct device *dev)
+static int __maybe_unused acp63_pdm_suspend(struct device *dev)
{
struct pdm_dev_data *adata;
adata = dev_get_drvdata(dev);
- acp62_disable_pdm_interrupts(adata->acp62_base);
+ acp63_disable_pdm_interrupts(adata->acp63_base);
return 0;
}
-static int __maybe_unused acp62_pdm_runtime_resume(struct device *dev)
+static int __maybe_unused acp63_pdm_runtime_resume(struct device *dev)
{
struct pdm_dev_data *adata;
adata = dev_get_drvdata(dev);
- acp62_enable_pdm_interrupts(adata->acp62_base);
+ acp63_enable_pdm_interrupts(adata->acp63_base);
return 0;
}
-static const struct dev_pm_ops acp62_pdm_pm_ops = {
- SET_RUNTIME_PM_OPS(acp62_pdm_suspend, acp62_pdm_runtime_resume, NULL)
- SET_SYSTEM_SLEEP_PM_OPS(acp62_pdm_suspend, acp62_pdm_resume)
+static const struct dev_pm_ops acp63_pdm_pm_ops = {
+ SET_RUNTIME_PM_OPS(acp63_pdm_suspend, acp63_pdm_runtime_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(acp63_pdm_suspend, acp63_pdm_resume)
};
-static struct platform_driver acp62_pdm_dma_driver = {
- .probe = acp62_pdm_audio_probe,
- .remove = acp62_pdm_audio_remove,
+static struct platform_driver acp63_pdm_dma_driver = {
+ .probe = acp63_pdm_audio_probe,
+ .remove = acp63_pdm_audio_remove,
.driver = {
.name = "acp_ps_pdm_dma",
- .pm = &acp62_pdm_pm_ops,
+ .pm = &acp63_pdm_pm_ops,
},
};
-module_platform_driver(acp62_pdm_dma_driver);
+module_platform_driver(acp63_pdm_dma_driver);
MODULE_AUTHOR("Syed.SabaKareem@amd.com");
MODULE_DESCRIPTION("AMD PINK SARDINE PDM Driver");
projects / linux.git / commitdiff