L: dri-devel@lists.freedesktop.org
S: Maintained
F: Documentation/devicetree/bindings/display/imx/
-F: drivers/gpu/drm/imx/
+F: drivers/gpu/drm/imx/ipuv3/
F: drivers/gpu/ipu-v3/
DRM DRIVERS FOR FREESCALE IMX BRIDGE
# SPDX-License-Identifier: GPL-2.0-only
-config DRM_IMX
- tristate "DRM Support for Freescale i.MX"
- select DRM_KMS_HELPER
- select VIDEOMODE_HELPERS
- select DRM_GEM_DMA_HELPER
- depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM || COMPILE_TEST)
- depends on IMX_IPUV3_CORE
- help
- enable i.MX graphics support
-
-config DRM_IMX_PARALLEL_DISPLAY
- tristate "Support for parallel displays"
- select DRM_PANEL
- depends on DRM_IMX
- select VIDEOMODE_HELPERS
-
-config DRM_IMX_TVE
- tristate "Support for TV and VGA displays"
- depends on DRM_IMX
- depends on COMMON_CLK
- select REGMAP_MMIO
- help
- Choose this to enable the internal Television Encoder (TVe)
- found on i.MX53 processors.
-
-config DRM_IMX_LDB
- tristate "Support for LVDS displays"
- depends on DRM_IMX && MFD_SYSCON
- depends on COMMON_CLK
- select DRM_PANEL
- help
- Choose this to enable the internal LVDS Display Bridge (LDB)
- found on i.MX53 and i.MX6 processors.
-
-config DRM_IMX_HDMI
- tristate "Freescale i.MX DRM HDMI"
- select DRM_DW_HDMI
- depends on DRM_IMX && OF
- help
- Choose this if you want to use HDMI on i.MX6.
source "drivers/gpu/drm/imx/dcss/Kconfig"
+source "drivers/gpu/drm/imx/ipuv3/Kconfig"
# SPDX-License-Identifier: GPL-2.0
-imxdrm-objs := imx-drm-core.o ipuv3-crtc.o ipuv3-plane.o
-
-obj-$(CONFIG_DRM_IMX) += imxdrm.o
-
-obj-$(CONFIG_DRM_IMX_PARALLEL_DISPLAY) += parallel-display.o
-obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
-obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
-
-obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
+obj-$(CONFIG_DRM_IMX) += ipuv3/
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
- *
- * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
- */
-
-#include <linux/component.h>
-#include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include <video/imx-ipu-v3.h>
-
-#include <drm/bridge/dw_hdmi.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_bridge.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_encoder.h>
-#include <drm/drm_managed.h>
-#include <drm/drm_of.h>
-#include <drm/drm_simple_kms_helper.h>
-
-#include "imx-drm.h"
-
-struct imx_hdmi;
-
-struct imx_hdmi_encoder {
- struct drm_encoder encoder;
- struct imx_hdmi *hdmi;
-};
-
-struct imx_hdmi {
- struct device *dev;
- struct drm_bridge *bridge;
- struct dw_hdmi *hdmi;
- struct regmap *regmap;
-};
-
-static inline struct imx_hdmi *enc_to_imx_hdmi(struct drm_encoder *e)
-{
- return container_of(e, struct imx_hdmi_encoder, encoder)->hdmi;
-}
-
-static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
- {
- 45250000, {
- { 0x01e0, 0x0000 },
- { 0x21e1, 0x0000 },
- { 0x41e2, 0x0000 }
- },
- }, {
- 92500000, {
- { 0x0140, 0x0005 },
- { 0x2141, 0x0005 },
- { 0x4142, 0x0005 },
- },
- }, {
- 148500000, {
- { 0x00a0, 0x000a },
- { 0x20a1, 0x000a },
- { 0x40a2, 0x000a },
- },
- }, {
- 216000000, {
- { 0x00a0, 0x000a },
- { 0x2001, 0x000f },
- { 0x4002, 0x000f },
- },
- }, {
- ~0UL, {
- { 0x0000, 0x0000 },
- { 0x0000, 0x0000 },
- { 0x0000, 0x0000 },
- },
- }
-};
-
-static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
- /* pixelclk bpp8 bpp10 bpp12 */
- {
- 54000000, { 0x091c, 0x091c, 0x06dc },
- }, {
- 58400000, { 0x091c, 0x06dc, 0x06dc },
- }, {
- 72000000, { 0x06dc, 0x06dc, 0x091c },
- }, {
- 74250000, { 0x06dc, 0x0b5c, 0x091c },
- }, {
- 118800000, { 0x091c, 0x091c, 0x06dc },
- }, {
- 216000000, { 0x06dc, 0x0b5c, 0x091c },
- }, {
- ~0UL, { 0x0000, 0x0000, 0x0000 },
- },
-};
-
-/*
- * Resistance term 133Ohm Cfg
- * PREEMP config 0.00
- * TX/CK level 10
- */
-static const struct dw_hdmi_phy_config imx_phy_config[] = {
- /*pixelclk symbol term vlev */
- { 216000000, 0x800d, 0x0005, 0x01ad},
- { ~0UL, 0x0000, 0x0000, 0x0000}
-};
-
-static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
-{
- struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
- int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
-
- regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
- IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
- mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
-}
-
-static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
-
- imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
- imx_crtc_state->di_hsync_pin = 2;
- imx_crtc_state->di_vsync_pin = 3;
-
- return 0;
-}
-
-static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
- .enable = dw_hdmi_imx_encoder_enable,
- .atomic_check = dw_hdmi_imx_atomic_check,
-};
-
-static enum drm_mode_status
-imx6q_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
- const struct drm_display_info *info,
- const struct drm_display_mode *mode)
-{
- if (mode->clock < 13500)
- return MODE_CLOCK_LOW;
- /* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
- if (mode->clock > 216000)
- return MODE_CLOCK_HIGH;
-
- return MODE_OK;
-}
-
-static enum drm_mode_status
-imx6dl_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
- const struct drm_display_info *info,
- const struct drm_display_mode *mode)
-{
- if (mode->clock < 13500)
- return MODE_CLOCK_LOW;
- /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
- if (mode->clock > 216000)
- return MODE_CLOCK_HIGH;
-
- return MODE_OK;
-}
-
-static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
- .mpll_cfg = imx_mpll_cfg,
- .cur_ctr = imx_cur_ctr,
- .phy_config = imx_phy_config,
- .mode_valid = imx6q_hdmi_mode_valid,
-};
-
-static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
- .mpll_cfg = imx_mpll_cfg,
- .cur_ctr = imx_cur_ctr,
- .phy_config = imx_phy_config,
- .mode_valid = imx6dl_hdmi_mode_valid,
-};
-
-static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
- { .compatible = "fsl,imx6q-hdmi",
- .data = &imx6q_hdmi_drv_data
- }, {
- .compatible = "fsl,imx6dl-hdmi",
- .data = &imx6dl_hdmi_drv_data
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
-
-static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
- void *data)
-{
- struct drm_device *drm = data;
- struct imx_hdmi_encoder *hdmi_encoder;
- struct drm_encoder *encoder;
- int ret;
-
- hdmi_encoder = drmm_simple_encoder_alloc(drm, struct imx_hdmi_encoder,
- encoder, DRM_MODE_ENCODER_TMDS);
- if (IS_ERR(hdmi_encoder))
- return PTR_ERR(hdmi_encoder);
-
- hdmi_encoder->hdmi = dev_get_drvdata(dev);
- encoder = &hdmi_encoder->encoder;
-
- ret = imx_drm_encoder_parse_of(drm, encoder, dev->of_node);
- if (ret)
- return ret;
-
- drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
-
- return drm_bridge_attach(encoder, hdmi_encoder->hdmi->bridge, NULL, 0);
-}
-
-static const struct component_ops dw_hdmi_imx_ops = {
- .bind = dw_hdmi_imx_bind,
-};
-
-static int dw_hdmi_imx_probe(struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node;
- const struct of_device_id *match = of_match_node(dw_hdmi_imx_dt_ids, np);
- struct imx_hdmi *hdmi;
- int ret;
-
- hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
- if (!hdmi)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, hdmi);
- hdmi->dev = &pdev->dev;
-
- hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
- if (IS_ERR(hdmi->regmap)) {
- dev_err(hdmi->dev, "Unable to get gpr\n");
- return PTR_ERR(hdmi->regmap);
- }
-
- hdmi->hdmi = dw_hdmi_probe(pdev, match->data);
- if (IS_ERR(hdmi->hdmi))
- return PTR_ERR(hdmi->hdmi);
-
- hdmi->bridge = of_drm_find_bridge(np);
- if (!hdmi->bridge) {
- dev_err(hdmi->dev, "Unable to find bridge\n");
- dw_hdmi_remove(hdmi->hdmi);
- return -ENODEV;
- }
-
- ret = component_add(&pdev->dev, &dw_hdmi_imx_ops);
- if (ret)
- dw_hdmi_remove(hdmi->hdmi);
-
- return ret;
-}
-
-static int dw_hdmi_imx_remove(struct platform_device *pdev)
-{
- struct imx_hdmi *hdmi = platform_get_drvdata(pdev);
-
- component_del(&pdev->dev, &dw_hdmi_imx_ops);
- dw_hdmi_remove(hdmi->hdmi);
-
- return 0;
-}
-
-static struct platform_driver dw_hdmi_imx_platform_driver = {
- .probe = dw_hdmi_imx_probe,
- .remove = dw_hdmi_imx_remove,
- .driver = {
- .name = "dwhdmi-imx",
- .of_match_table = dw_hdmi_imx_dt_ids,
- },
-};
-
-module_platform_driver(dw_hdmi_imx_platform_driver);
-
-MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
-MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
-MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:dwhdmi-imx");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Freescale i.MX drm driver
- *
- * Copyright (C) 2011 Sascha Hauer, Pengutronix
- */
-
-#include <linux/component.h>
-#include <linux/device.h>
-#include <linux/dma-buf.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-
-#include <video/imx-ipu-v3.h>
-
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_drv.h>
-#include <drm/drm_fbdev_generic.h>
-#include <drm/drm_gem_dma_helper.h>
-#include <drm/drm_gem_framebuffer_helper.h>
-#include <drm/drm_managed.h>
-#include <drm/drm_of.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_vblank.h>
-
-#include "imx-drm.h"
-#include "ipuv3-plane.h"
-
-#define MAX_CRTC 4
-
-static int legacyfb_depth = 16;
-module_param(legacyfb_depth, int, 0444);
-
-DEFINE_DRM_GEM_DMA_FOPS(imx_drm_driver_fops);
-
-void imx_drm_connector_destroy(struct drm_connector *connector)
-{
- drm_connector_unregister(connector);
- drm_connector_cleanup(connector);
-}
-EXPORT_SYMBOL_GPL(imx_drm_connector_destroy);
-
-static int imx_drm_atomic_check(struct drm_device *dev,
- struct drm_atomic_state *state)
-{
- int ret;
-
- ret = drm_atomic_helper_check(dev, state);
- if (ret)
- return ret;
-
- /*
- * Check modeset again in case crtc_state->mode_changed is
- * updated in plane's ->atomic_check callback.
- */
- ret = drm_atomic_helper_check_modeset(dev, state);
- if (ret)
- return ret;
-
- /* Assign PRG/PRE channels and check if all constrains are satisfied. */
- ret = ipu_planes_assign_pre(dev, state);
- if (ret)
- return ret;
-
- return ret;
-}
-
-static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
- .fb_create = drm_gem_fb_create,
- .atomic_check = imx_drm_atomic_check,
- .atomic_commit = drm_atomic_helper_commit,
-};
-
-static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
-{
- struct drm_device *dev = state->dev;
- struct drm_plane *plane;
- struct drm_plane_state *old_plane_state, *new_plane_state;
- bool plane_disabling = false;
- int i;
-
- drm_atomic_helper_commit_modeset_disables(dev, state);
-
- drm_atomic_helper_commit_planes(dev, state,
- DRM_PLANE_COMMIT_ACTIVE_ONLY |
- DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET);
-
- drm_atomic_helper_commit_modeset_enables(dev, state);
-
- for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
- if (drm_atomic_plane_disabling(old_plane_state, new_plane_state))
- plane_disabling = true;
- }
-
- /*
- * The flip done wait is only strictly required by imx-drm if a deferred
- * plane disable is in-flight. As the core requires blocking commits
- * to wait for the flip it is done here unconditionally. This keeps the
- * workitem around a bit longer than required for the majority of
- * non-blocking commits, but we accept that for the sake of simplicity.
- */
- drm_atomic_helper_wait_for_flip_done(dev, state);
-
- if (plane_disabling) {
- for_each_old_plane_in_state(state, plane, old_plane_state, i)
- ipu_plane_disable_deferred(plane);
-
- }
-
- drm_atomic_helper_commit_hw_done(state);
-}
-
-static const struct drm_mode_config_helper_funcs imx_drm_mode_config_helpers = {
- .atomic_commit_tail = imx_drm_atomic_commit_tail,
-};
-
-
-int imx_drm_encoder_parse_of(struct drm_device *drm,
- struct drm_encoder *encoder, struct device_node *np)
-{
- uint32_t crtc_mask = drm_of_find_possible_crtcs(drm, np);
-
- /*
- * If we failed to find the CRTC(s) which this encoder is
- * supposed to be connected to, it's because the CRTC has
- * not been registered yet. Defer probing, and hope that
- * the required CRTC is added later.
- */
- if (crtc_mask == 0)
- return -EPROBE_DEFER;
-
- encoder->possible_crtcs = crtc_mask;
-
- /* FIXME: cloning support not clear, disable it all for now */
- encoder->possible_clones = 0;
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of);
-
-static const struct drm_ioctl_desc imx_drm_ioctls[] = {
- /* none so far */
-};
-
-static int imx_drm_dumb_create(struct drm_file *file_priv,
- struct drm_device *drm,
- struct drm_mode_create_dumb *args)
-{
- u32 width = args->width;
- int ret;
-
- args->width = ALIGN(width, 8);
-
- ret = drm_gem_dma_dumb_create(file_priv, drm, args);
- if (ret)
- return ret;
-
- args->width = width;
- return ret;
-}
-
-static const struct drm_driver imx_drm_driver = {
- .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
- DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(imx_drm_dumb_create),
- .ioctls = imx_drm_ioctls,
- .num_ioctls = ARRAY_SIZE(imx_drm_ioctls),
- .fops = &imx_drm_driver_fops,
- .name = "imx-drm",
- .desc = "i.MX DRM graphics",
- .date = "20120507",
- .major = 1,
- .minor = 0,
- .patchlevel = 0,
-};
-
-static int compare_of(struct device *dev, void *data)
-{
- struct device_node *np = data;
-
- /* Special case for DI, dev->of_node may not be set yet */
- if (strcmp(dev->driver->name, "imx-ipuv3-crtc") == 0) {
- struct ipu_client_platformdata *pdata = dev->platform_data;
-
- return pdata->of_node == np;
- }
-
- /* Special case for LDB, one device for two channels */
- if (of_node_name_eq(np, "lvds-channel")) {
- np = of_get_parent(np);
- of_node_put(np);
- }
-
- return dev->of_node == np;
-}
-
-static int imx_drm_bind(struct device *dev)
-{
- struct drm_device *drm;
- int ret;
-
- drm = drm_dev_alloc(&imx_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
-
- /*
- * set max width and height as default value(4096x4096).
- * this value would be used to check framebuffer size limitation
- * at drm_mode_addfb().
- */
- drm->mode_config.min_width = 1;
- drm->mode_config.min_height = 1;
- drm->mode_config.max_width = 4096;
- drm->mode_config.max_height = 4096;
- drm->mode_config.funcs = &imx_drm_mode_config_funcs;
- drm->mode_config.helper_private = &imx_drm_mode_config_helpers;
- drm->mode_config.normalize_zpos = true;
-
- ret = drmm_mode_config_init(drm);
- if (ret)
- goto err_kms;
-
- ret = drm_vblank_init(drm, MAX_CRTC);
- if (ret)
- goto err_kms;
-
- dev_set_drvdata(dev, drm);
-
- /* Now try and bind all our sub-components */
- ret = component_bind_all(dev, drm);
- if (ret)
- goto err_kms;
-
- drm_mode_config_reset(drm);
-
- /*
- * All components are now initialised, so setup the fb helper.
- * The fb helper takes copies of key hardware information, so the
- * crtcs/connectors/encoders must not change after this point.
- */
- if (legacyfb_depth != 16 && legacyfb_depth != 32) {
- dev_warn(dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n");
- legacyfb_depth = 16;
- }
-
- drm_kms_helper_poll_init(drm);
-
- ret = drm_dev_register(drm, 0);
- if (ret)
- goto err_poll_fini;
-
- drm_fbdev_generic_setup(drm, legacyfb_depth);
-
- return 0;
-
-err_poll_fini:
- drm_kms_helper_poll_fini(drm);
- component_unbind_all(drm->dev, drm);
-err_kms:
- drm_dev_put(drm);
-
- return ret;
-}
-
-static void imx_drm_unbind(struct device *dev)
-{
- struct drm_device *drm = dev_get_drvdata(dev);
-
- drm_dev_unregister(drm);
-
- drm_kms_helper_poll_fini(drm);
-
- component_unbind_all(drm->dev, drm);
-
- drm_dev_put(drm);
-
- dev_set_drvdata(dev, NULL);
-}
-
-static const struct component_master_ops imx_drm_ops = {
- .bind = imx_drm_bind,
- .unbind = imx_drm_unbind,
-};
-
-static int imx_drm_platform_probe(struct platform_device *pdev)
-{
- int ret = drm_of_component_probe(&pdev->dev, compare_of, &imx_drm_ops);
-
- if (!ret)
- ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
-
- return ret;
-}
-
-static int imx_drm_platform_remove(struct platform_device *pdev)
-{
- component_master_del(&pdev->dev, &imx_drm_ops);
- return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int imx_drm_suspend(struct device *dev)
-{
- struct drm_device *drm_dev = dev_get_drvdata(dev);
-
- return drm_mode_config_helper_suspend(drm_dev);
-}
-
-static int imx_drm_resume(struct device *dev)
-{
- struct drm_device *drm_dev = dev_get_drvdata(dev);
-
- return drm_mode_config_helper_resume(drm_dev);
-}
-#endif
-
-static SIMPLE_DEV_PM_OPS(imx_drm_pm_ops, imx_drm_suspend, imx_drm_resume);
-
-static const struct of_device_id imx_drm_dt_ids[] = {
- { .compatible = "fsl,imx-display-subsystem", },
- { /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(of, imx_drm_dt_ids);
-
-static struct platform_driver imx_drm_pdrv = {
- .probe = imx_drm_platform_probe,
- .remove = imx_drm_platform_remove,
- .driver = {
- .name = "imx-drm",
- .pm = &imx_drm_pm_ops,
- .of_match_table = imx_drm_dt_ids,
- },
-};
-
-static struct platform_driver * const drivers[] = {
- &imx_drm_pdrv,
- &ipu_drm_driver,
-};
-
-static int __init imx_drm_init(void)
-{
- if (drm_firmware_drivers_only())
- return -ENODEV;
-
- return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
-}
-module_init(imx_drm_init);
-
-static void __exit imx_drm_exit(void)
-{
- platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
-}
-module_exit(imx_drm_exit);
-
-MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
-MODULE_DESCRIPTION("i.MX drm driver core");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _IMX_DRM_H_
-#define _IMX_DRM_H_
-
-struct device_node;
-struct drm_crtc;
-struct drm_connector;
-struct drm_device;
-struct drm_display_mode;
-struct drm_encoder;
-struct drm_framebuffer;
-struct drm_plane;
-struct platform_device;
-
-struct imx_crtc_state {
- struct drm_crtc_state base;
- u32 bus_format;
- u32 bus_flags;
- int di_hsync_pin;
- int di_vsync_pin;
-};
-
-static inline struct imx_crtc_state *to_imx_crtc_state(struct drm_crtc_state *s)
-{
- return container_of(s, struct imx_crtc_state, base);
-}
-int imx_drm_init_drm(struct platform_device *pdev,
- int preferred_bpp);
-int imx_drm_exit_drm(void);
-
-extern struct platform_driver ipu_drm_driver;
-
-void imx_drm_mode_config_init(struct drm_device *drm);
-
-struct drm_gem_dma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
-
-int imx_drm_encoder_parse_of(struct drm_device *drm,
- struct drm_encoder *encoder, struct device_node *np);
-
-void imx_drm_connector_destroy(struct drm_connector *connector);
-
-int ipu_planes_assign_pre(struct drm_device *dev,
- struct drm_atomic_state *state);
-
-#endif /* _IMX_DRM_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * i.MX drm driver - LVDS display bridge
- *
- * Copyright (C) 2012 Sascha Hauer, Pengutronix
- */
-
-#include <linux/clk.h>
-#include <linux/component.h>
-#include <linux/i2c.h>
-#include <linux/media-bus-format.h>
-#include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/of_graph.h>
-#include <linux/regmap.h>
-#include <linux/videodev2.h>
-
-#include <video/of_display_timing.h>
-#include <video/of_videomode.h>
-
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_bridge.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_managed.h>
-#include <drm/drm_of.h>
-#include <drm/drm_panel.h>
-#include <drm/drm_print.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_simple_kms_helper.h>
-
-#include "imx-drm.h"
-
-#define DRIVER_NAME "imx-ldb"
-
-#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
-#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
-#define LDB_CH0_MODE_EN_MASK (3 << 0)
-#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
-#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
-#define LDB_CH1_MODE_EN_MASK (3 << 2)
-#define LDB_SPLIT_MODE_EN (1 << 4)
-#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
-#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
-#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
-#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
-#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
-#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
-#define LDB_BGREF_RMODE_INT (1 << 15)
-
-struct imx_ldb_channel;
-
-struct imx_ldb_encoder {
- struct drm_connector connector;
- struct drm_encoder encoder;
- struct imx_ldb_channel *channel;
-};
-
-struct imx_ldb;
-
-struct imx_ldb_channel {
- struct imx_ldb *ldb;
-
- /* Defines what is connected to the ldb, only one at a time */
- struct drm_panel *panel;
- struct drm_bridge *bridge;
-
- struct device_node *child;
- struct i2c_adapter *ddc;
- int chno;
- void *edid;
- struct drm_display_mode mode;
- int mode_valid;
- u32 bus_format;
- u32 bus_flags;
-};
-
-static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
-{
- return container_of(c, struct imx_ldb_encoder, connector)->channel;
-}
-
-static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
-{
- return container_of(e, struct imx_ldb_encoder, encoder)->channel;
-}
-
-struct bus_mux {
- int reg;
- int shift;
- int mask;
-};
-
-struct imx_ldb {
- struct regmap *regmap;
- struct device *dev;
- struct imx_ldb_channel channel[2];
- struct clk *clk[2]; /* our own clock */
- struct clk *clk_sel[4]; /* parent of display clock */
- struct clk *clk_parent[4]; /* original parent of clk_sel */
- struct clk *clk_pll[2]; /* upstream clock we can adjust */
- u32 ldb_ctrl;
- const struct bus_mux *lvds_mux;
-};
-
-static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
- u32 bus_format)
-{
- struct imx_ldb *ldb = imx_ldb_ch->ldb;
- int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
-
- switch (bus_format) {
- case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
- break;
- case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
- if (imx_ldb_ch->chno == 0 || dual)
- ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
- if (imx_ldb_ch->chno == 1 || dual)
- ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
- break;
- case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
- if (imx_ldb_ch->chno == 0 || dual)
- ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
- LDB_BIT_MAP_CH0_JEIDA;
- if (imx_ldb_ch->chno == 1 || dual)
- ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
- LDB_BIT_MAP_CH1_JEIDA;
- break;
- }
-}
-
-static int imx_ldb_connector_get_modes(struct drm_connector *connector)
-{
- struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
- int num_modes;
-
- num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);
- if (num_modes > 0)
- return num_modes;
-
- if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
- imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
-
- if (imx_ldb_ch->edid) {
- drm_connector_update_edid_property(connector,
- imx_ldb_ch->edid);
- num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
- }
-
- if (imx_ldb_ch->mode_valid) {
- struct drm_display_mode *mode;
-
- mode = drm_mode_duplicate(connector->dev, &imx_ldb_ch->mode);
- if (!mode)
- return -EINVAL;
- mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
- drm_mode_probed_add(connector, mode);
- num_modes++;
- }
-
- return num_modes;
-}
-
-static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
- unsigned long serial_clk, unsigned long di_clk)
-{
- int ret;
-
- dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
- clk_get_rate(ldb->clk_pll[chno]), serial_clk);
- clk_set_rate(ldb->clk_pll[chno], serial_clk);
-
- dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
- clk_get_rate(ldb->clk_pll[chno]));
-
- dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
- clk_get_rate(ldb->clk[chno]),
- (long int)di_clk);
- clk_set_rate(ldb->clk[chno], di_clk);
-
- dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
- clk_get_rate(ldb->clk[chno]));
-
- /* set display clock mux to LDB input clock */
- ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
- if (ret)
- dev_err(ldb->dev,
- "unable to set di%d parent clock to ldb_di%d\n", mux,
- chno);
-}
-
-static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
-{
- struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
- struct imx_ldb *ldb = imx_ldb_ch->ldb;
- int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
- int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
-
- if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
- dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
- return;
- }
-
- drm_panel_prepare(imx_ldb_ch->panel);
-
- if (dual) {
- clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
- clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
-
- clk_prepare_enable(ldb->clk[0]);
- clk_prepare_enable(ldb->clk[1]);
- } else {
- clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
- }
-
- if (imx_ldb_ch == &ldb->channel[0] || dual) {
- ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
- if (mux == 0 || ldb->lvds_mux)
- ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
- else if (mux == 1)
- ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
- }
- if (imx_ldb_ch == &ldb->channel[1] || dual) {
- ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
- if (mux == 1 || ldb->lvds_mux)
- ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
- else if (mux == 0)
- ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
- }
-
- if (ldb->lvds_mux) {
- const struct bus_mux *lvds_mux = NULL;
-
- if (imx_ldb_ch == &ldb->channel[0])
- lvds_mux = &ldb->lvds_mux[0];
- else if (imx_ldb_ch == &ldb->channel[1])
- lvds_mux = &ldb->lvds_mux[1];
-
- regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
- mux << lvds_mux->shift);
- }
-
- regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
-
- drm_panel_enable(imx_ldb_ch->panel);
-}
-
-static void
-imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *connector_state)
-{
- struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
- struct drm_display_mode *mode = &crtc_state->adjusted_mode;
- struct imx_ldb *ldb = imx_ldb_ch->ldb;
- int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
- unsigned long serial_clk;
- unsigned long di_clk = mode->clock * 1000;
- int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
- u32 bus_format = imx_ldb_ch->bus_format;
-
- if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
- dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
- return;
- }
-
- if (mode->clock > 170000) {
- dev_warn(ldb->dev,
- "%s: mode exceeds 170 MHz pixel clock\n", __func__);
- }
- if (mode->clock > 85000 && !dual) {
- dev_warn(ldb->dev,
- "%s: mode exceeds 85 MHz pixel clock\n", __func__);
- }
-
- if (!IS_ALIGNED(mode->hdisplay, 8)) {
- dev_warn(ldb->dev,
- "%s: hdisplay does not align to 8 byte\n", __func__);
- }
-
- if (dual) {
- serial_clk = 3500UL * mode->clock;
- imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
- imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
- } else {
- serial_clk = 7000UL * mode->clock;
- imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
- di_clk);
- }
-
- /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
- if (imx_ldb_ch == &ldb->channel[0] || dual) {
- if (mode->flags & DRM_MODE_FLAG_NVSYNC)
- ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
- else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
- ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
- }
- if (imx_ldb_ch == &ldb->channel[1] || dual) {
- if (mode->flags & DRM_MODE_FLAG_NVSYNC)
- ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
- else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
- ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
- }
-
- if (!bus_format) {
- struct drm_connector *connector = connector_state->connector;
- struct drm_display_info *di = &connector->display_info;
-
- if (di->num_bus_formats)
- bus_format = di->bus_formats[0];
- }
- imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
-}
-
-static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
-{
- struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
- struct imx_ldb *ldb = imx_ldb_ch->ldb;
- int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
- int mux, ret;
-
- drm_panel_disable(imx_ldb_ch->panel);
-
- if (imx_ldb_ch == &ldb->channel[0] || dual)
- ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
- if (imx_ldb_ch == &ldb->channel[1] || dual)
- ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
-
- regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
-
- if (dual) {
- clk_disable_unprepare(ldb->clk[0]);
- clk_disable_unprepare(ldb->clk[1]);
- }
-
- if (ldb->lvds_mux) {
- const struct bus_mux *lvds_mux = NULL;
-
- if (imx_ldb_ch == &ldb->channel[0])
- lvds_mux = &ldb->lvds_mux[0];
- else if (imx_ldb_ch == &ldb->channel[1])
- lvds_mux = &ldb->lvds_mux[1];
-
- regmap_read(ldb->regmap, lvds_mux->reg, &mux);
- mux &= lvds_mux->mask;
- mux >>= lvds_mux->shift;
- } else {
- mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
- }
-
- /* set display clock mux back to original input clock */
- ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
- if (ret)
- dev_err(ldb->dev,
- "unable to set di%d parent clock to original parent\n",
- mux);
-
- drm_panel_unprepare(imx_ldb_ch->panel);
-}
-
-static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
- struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
- struct drm_display_info *di = &conn_state->connector->display_info;
- u32 bus_format = imx_ldb_ch->bus_format;
-
- /* Bus format description in DT overrides connector display info. */
- if (!bus_format && di->num_bus_formats) {
- bus_format = di->bus_formats[0];
- imx_crtc_state->bus_flags = di->bus_flags;
- } else {
- bus_format = imx_ldb_ch->bus_format;
- imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
- }
- switch (bus_format) {
- case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
- imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
- break;
- case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
- case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
- imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
- break;
- default:
- return -EINVAL;
- }
-
- imx_crtc_state->di_hsync_pin = 2;
- imx_crtc_state->di_vsync_pin = 3;
-
- return 0;
-}
-
-
-static const struct drm_connector_funcs imx_ldb_connector_funcs = {
- .fill_modes = drm_helper_probe_single_connector_modes,
- .destroy = imx_drm_connector_destroy,
- .reset = drm_atomic_helper_connector_reset,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
- .get_modes = imx_ldb_connector_get_modes,
-};
-
-static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
- .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
- .enable = imx_ldb_encoder_enable,
- .disable = imx_ldb_encoder_disable,
- .atomic_check = imx_ldb_encoder_atomic_check,
-};
-
-static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
-{
- char clkname[16];
-
- snprintf(clkname, sizeof(clkname), "di%d", chno);
- ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
- if (IS_ERR(ldb->clk[chno]))
- return PTR_ERR(ldb->clk[chno]);
-
- snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
- ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
-
- return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
-}
-
-static int imx_ldb_register(struct drm_device *drm,
- struct imx_ldb_channel *imx_ldb_ch)
-{
- struct imx_ldb *ldb = imx_ldb_ch->ldb;
- struct imx_ldb_encoder *ldb_encoder;
- struct drm_connector *connector;
- struct drm_encoder *encoder;
- int ret;
-
- ldb_encoder = drmm_simple_encoder_alloc(drm, struct imx_ldb_encoder,
- encoder, DRM_MODE_ENCODER_LVDS);
- if (IS_ERR(ldb_encoder))
- return PTR_ERR(ldb_encoder);
-
- ldb_encoder->channel = imx_ldb_ch;
- connector = &ldb_encoder->connector;
- encoder = &ldb_encoder->encoder;
-
- ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
- if (ret)
- return ret;
-
- ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
- if (ret)
- return ret;
-
- if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
- ret = imx_ldb_get_clk(ldb, 1);
- if (ret)
- return ret;
- }
-
- drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
-
- if (imx_ldb_ch->bridge) {
- ret = drm_bridge_attach(encoder, imx_ldb_ch->bridge, NULL, 0);
- if (ret)
- return ret;
- } else {
- /*
- * We want to add the connector whenever there is no bridge
- * that brings its own, not only when there is a panel. For
- * historical reasons, the ldb driver can also work without
- * a panel.
- */
- drm_connector_helper_add(connector,
- &imx_ldb_connector_helper_funcs);
- drm_connector_init_with_ddc(drm, connector,
- &imx_ldb_connector_funcs,
- DRM_MODE_CONNECTOR_LVDS,
- imx_ldb_ch->ddc);
- drm_connector_attach_encoder(connector, encoder);
- }
-
- return 0;
-}
-
-struct imx_ldb_bit_mapping {
- u32 bus_format;
- u32 datawidth;
- const char * const mapping;
-};
-
-static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
- { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
- { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
- { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
-};
-
-static u32 of_get_bus_format(struct device *dev, struct device_node *np)
-{
- const char *bm;
- u32 datawidth = 0;
- int ret, i;
-
- ret = of_property_read_string(np, "fsl,data-mapping", &bm);
- if (ret < 0)
- return ret;
-
- of_property_read_u32(np, "fsl,data-width", &datawidth);
-
- for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
- if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
- datawidth == imx_ldb_bit_mappings[i].datawidth)
- return imx_ldb_bit_mappings[i].bus_format;
- }
-
- dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
-
- return -ENOENT;
-}
-
-static struct bus_mux imx6q_lvds_mux[2] = {
- {
- .reg = IOMUXC_GPR3,
- .shift = 6,
- .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
- }, {
- .reg = IOMUXC_GPR3,
- .shift = 8,
- .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
- }
-};
-
-/*
- * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
- * of_match_device will walk through this list and take the first entry
- * matching any of its compatible values. Therefore, the more generic
- * entries (in this case fsl,imx53-ldb) need to be ordered last.
- */
-static const struct of_device_id imx_ldb_dt_ids[] = {
- { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
- { .compatible = "fsl,imx53-ldb", .data = NULL, },
- { }
-};
-MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
-
-static int imx_ldb_panel_ddc(struct device *dev,
- struct imx_ldb_channel *channel, struct device_node *child)
-{
- struct device_node *ddc_node;
- const u8 *edidp;
- int ret;
-
- ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
- if (ddc_node) {
- channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
- of_node_put(ddc_node);
- if (!channel->ddc) {
- dev_warn(dev, "failed to get ddc i2c adapter\n");
- return -EPROBE_DEFER;
- }
- }
-
- if (!channel->ddc) {
- int edid_len;
-
- /* if no DDC available, fallback to hardcoded EDID */
- dev_dbg(dev, "no ddc available\n");
-
- edidp = of_get_property(child, "edid", &edid_len);
- if (edidp) {
- channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
- if (!channel->edid)
- return -ENOMEM;
- } else if (!channel->panel) {
- /* fallback to display-timings node */
- ret = of_get_drm_display_mode(child,
- &channel->mode,
- &channel->bus_flags,
- OF_USE_NATIVE_MODE);
- if (!ret)
- channel->mode_valid = 1;
- }
- }
- return 0;
-}
-
-static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
-{
- struct drm_device *drm = data;
- struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
- int ret;
- int i;
-
- for (i = 0; i < 2; i++) {
- struct imx_ldb_channel *channel = &imx_ldb->channel[i];
-
- if (!channel->ldb)
- continue;
-
- ret = imx_ldb_register(drm, channel);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static const struct component_ops imx_ldb_ops = {
- .bind = imx_ldb_bind,
-};
-
-static int imx_ldb_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- const struct of_device_id *of_id = of_match_device(imx_ldb_dt_ids, dev);
- struct device_node *child;
- struct imx_ldb *imx_ldb;
- int dual;
- int ret;
- int i;
-
- imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
- if (!imx_ldb)
- return -ENOMEM;
-
- imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
- if (IS_ERR(imx_ldb->regmap)) {
- dev_err(dev, "failed to get parent regmap\n");
- return PTR_ERR(imx_ldb->regmap);
- }
-
- /* disable LDB by resetting the control register to POR default */
- regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
-
- imx_ldb->dev = dev;
-
- if (of_id)
- imx_ldb->lvds_mux = of_id->data;
-
- dual = of_property_read_bool(np, "fsl,dual-channel");
- if (dual)
- imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
-
- /*
- * There are three different possible clock mux configurations:
- * i.MX53: ipu1_di0_sel, ipu1_di1_sel
- * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
- * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
- * Map them all to di0_sel...di3_sel.
- */
- for (i = 0; i < 4; i++) {
- char clkname[16];
-
- sprintf(clkname, "di%d_sel", i);
- imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
- if (IS_ERR(imx_ldb->clk_sel[i])) {
- ret = PTR_ERR(imx_ldb->clk_sel[i]);
- imx_ldb->clk_sel[i] = NULL;
- break;
- }
-
- imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
- }
- if (i == 0)
- return ret;
-
- for_each_child_of_node(np, child) {
- struct imx_ldb_channel *channel;
- int bus_format;
-
- ret = of_property_read_u32(child, "reg", &i);
- if (ret || i < 0 || i > 1) {
- ret = -EINVAL;
- goto free_child;
- }
-
- if (!of_device_is_available(child))
- continue;
-
- if (dual && i > 0) {
- dev_warn(dev, "dual-channel mode, ignoring second output\n");
- continue;
- }
-
- channel = &imx_ldb->channel[i];
- channel->ldb = imx_ldb;
- channel->chno = i;
-
- /*
- * The output port is port@4 with an external 4-port mux or
- * port@2 with the internal 2-port mux.
- */
- ret = drm_of_find_panel_or_bridge(child,
- imx_ldb->lvds_mux ? 4 : 2, 0,
- &channel->panel, &channel->bridge);
- if (ret && ret != -ENODEV)
- goto free_child;
-
- /* panel ddc only if there is no bridge */
- if (!channel->bridge) {
- ret = imx_ldb_panel_ddc(dev, channel, child);
- if (ret)
- goto free_child;
- }
-
- bus_format = of_get_bus_format(dev, child);
- if (bus_format == -EINVAL) {
- /*
- * If no bus format was specified in the device tree,
- * we can still get it from the connected panel later.
- */
- if (channel->panel && channel->panel->funcs &&
- channel->panel->funcs->get_modes)
- bus_format = 0;
- }
- if (bus_format < 0) {
- dev_err(dev, "could not determine data mapping: %d\n",
- bus_format);
- ret = bus_format;
- goto free_child;
- }
- channel->bus_format = bus_format;
- channel->child = child;
- }
-
- platform_set_drvdata(pdev, imx_ldb);
-
- return component_add(&pdev->dev, &imx_ldb_ops);
-
-free_child:
- of_node_put(child);
- return ret;
-}
-
-static int imx_ldb_remove(struct platform_device *pdev)
-{
- struct imx_ldb *imx_ldb = platform_get_drvdata(pdev);
- int i;
-
- for (i = 0; i < 2; i++) {
- struct imx_ldb_channel *channel = &imx_ldb->channel[i];
-
- kfree(channel->edid);
- i2c_put_adapter(channel->ddc);
- }
-
- component_del(&pdev->dev, &imx_ldb_ops);
- return 0;
-}
-
-static struct platform_driver imx_ldb_driver = {
- .probe = imx_ldb_probe,
- .remove = imx_ldb_remove,
- .driver = {
- .of_match_table = imx_ldb_dt_ids,
- .name = DRIVER_NAME,
- },
-};
-
-module_platform_driver(imx_ldb_driver);
-
-MODULE_DESCRIPTION("i.MX LVDS driver");
-MODULE_AUTHOR("Sascha Hauer, Pengutronix");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRIVER_NAME);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * i.MX drm driver - Television Encoder (TVEv2)
- *
- * Copyright (C) 2013 Philipp Zabel, Pengutronix
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-#include <linux/component.h>
-#include <linux/i2c.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/regulator/consumer.h>
-#include <linux/videodev2.h>
-
-#include <video/imx-ipu-v3.h>
-
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_managed.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_simple_kms_helper.h>
-
-#include "imx-drm.h"
-
-#define TVE_COM_CONF_REG 0x00
-#define TVE_TVDAC0_CONT_REG 0x28
-#define TVE_TVDAC1_CONT_REG 0x2c
-#define TVE_TVDAC2_CONT_REG 0x30
-#define TVE_CD_CONT_REG 0x34
-#define TVE_INT_CONT_REG 0x64
-#define TVE_STAT_REG 0x68
-#define TVE_TST_MODE_REG 0x6c
-#define TVE_MV_CONT_REG 0xdc
-
-/* TVE_COM_CONF_REG */
-#define TVE_SYNC_CH_2_EN BIT(22)
-#define TVE_SYNC_CH_1_EN BIT(21)
-#define TVE_SYNC_CH_0_EN BIT(20)
-#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
-#define TVE_TV_OUT_DISABLE (0x0 << 12)
-#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
-#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
-#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
-#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
-#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
-#define TVE_TV_OUT_YPBPR (0x6 << 12)
-#define TVE_TV_OUT_RGB (0x7 << 12)
-#define TVE_TV_STAND_MASK (0xf << 8)
-#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
-#define TVE_P2I_CONV_EN BIT(7)
-#define TVE_INP_VIDEO_FORM BIT(6)
-#define TVE_INP_YCBCR_422 (0x0 << 6)
-#define TVE_INP_YCBCR_444 (0x1 << 6)
-#define TVE_DATA_SOURCE_MASK (0x3 << 4)
-#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
-#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
-#define TVE_DATA_SOURCE_EXT (0x2 << 4)
-#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
-#define TVE_IPU_CLK_EN_OFS 3
-#define TVE_IPU_CLK_EN BIT(3)
-#define TVE_DAC_SAMP_RATE_OFS 1
-#define TVE_DAC_SAMP_RATE_WIDTH 2
-#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
-#define TVE_DAC_FULL_RATE (0x0 << 1)
-#define TVE_DAC_DIV2_RATE (0x1 << 1)
-#define TVE_DAC_DIV4_RATE (0x2 << 1)
-#define TVE_EN BIT(0)
-
-/* TVE_TVDACx_CONT_REG */
-#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
-
-/* TVE_CD_CONT_REG */
-#define TVE_CD_CH_2_SM_EN BIT(22)
-#define TVE_CD_CH_1_SM_EN BIT(21)
-#define TVE_CD_CH_0_SM_EN BIT(20)
-#define TVE_CD_CH_2_LM_EN BIT(18)
-#define TVE_CD_CH_1_LM_EN BIT(17)
-#define TVE_CD_CH_0_LM_EN BIT(16)
-#define TVE_CD_CH_2_REF_LVL BIT(10)
-#define TVE_CD_CH_1_REF_LVL BIT(9)
-#define TVE_CD_CH_0_REF_LVL BIT(8)
-#define TVE_CD_EN BIT(0)
-
-/* TVE_INT_CONT_REG */
-#define TVE_FRAME_END_IEN BIT(13)
-#define TVE_CD_MON_END_IEN BIT(2)
-#define TVE_CD_SM_IEN BIT(1)
-#define TVE_CD_LM_IEN BIT(0)
-
-/* TVE_TST_MODE_REG */
-#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
-
-#define IMX_TVE_DAC_VOLTAGE 2750000
-
-enum {
- TVE_MODE_TVOUT,
- TVE_MODE_VGA,
-};
-
-struct imx_tve_encoder {
- struct drm_connector connector;
- struct drm_encoder encoder;
- struct imx_tve *tve;
-};
-
-struct imx_tve {
- struct device *dev;
- int mode;
- int di_hsync_pin;
- int di_vsync_pin;
-
- struct regmap *regmap;
- struct regulator *dac_reg;
- struct i2c_adapter *ddc;
- struct clk *clk;
- struct clk *di_sel_clk;
- struct clk_hw clk_hw_di;
- struct clk *di_clk;
-};
-
-static inline struct imx_tve *con_to_tve(struct drm_connector *c)
-{
- return container_of(c, struct imx_tve_encoder, connector)->tve;
-}
-
-static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
-{
- return container_of(e, struct imx_tve_encoder, encoder)->tve;
-}
-
-static void tve_enable(struct imx_tve *tve)
-{
- clk_prepare_enable(tve->clk);
- regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
-
- /* clear interrupt status register */
- regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
-
- /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
- if (tve->mode == TVE_MODE_VGA)
- regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
- else
- regmap_write(tve->regmap, TVE_INT_CONT_REG,
- TVE_CD_SM_IEN |
- TVE_CD_LM_IEN |
- TVE_CD_MON_END_IEN);
-}
-
-static void tve_disable(struct imx_tve *tve)
-{
- regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
- clk_disable_unprepare(tve->clk);
-}
-
-static int tve_setup_tvout(struct imx_tve *tve)
-{
- return -ENOTSUPP;
-}
-
-static int tve_setup_vga(struct imx_tve *tve)
-{
- unsigned int mask;
- unsigned int val;
- int ret;
-
- /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
- ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
- TVE_TVDAC_GAIN_MASK, 0x0a);
- if (ret)
- return ret;
-
- ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
- TVE_TVDAC_GAIN_MASK, 0x0a);
- if (ret)
- return ret;
-
- ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
- TVE_TVDAC_GAIN_MASK, 0x0a);
- if (ret)
- return ret;
-
- /* set configuration register */
- mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
- val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
- mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
- val |= TVE_TV_STAND_HD_1080P30 | 0;
- mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
- val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
- ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
- if (ret)
- return ret;
-
- /* set test mode (as documented) */
- return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
- TVE_TVDAC_TEST_MODE_MASK, 1);
-}
-
-static int imx_tve_connector_get_modes(struct drm_connector *connector)
-{
- struct imx_tve *tve = con_to_tve(connector);
- struct edid *edid;
- int ret = 0;
-
- if (!tve->ddc)
- return 0;
-
- edid = drm_get_edid(connector, tve->ddc);
- if (edid) {
- drm_connector_update_edid_property(connector, edid);
- ret = drm_add_edid_modes(connector, edid);
- kfree(edid);
- }
-
- return ret;
-}
-
-static enum drm_mode_status
-imx_tve_connector_mode_valid(struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- struct imx_tve *tve = con_to_tve(connector);
- unsigned long rate;
-
- /* pixel clock with 2x oversampling */
- rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
- if (rate == mode->clock)
- return MODE_OK;
-
- /* pixel clock without oversampling */
- rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
- if (rate == mode->clock)
- return MODE_OK;
-
- dev_warn(tve->dev, "ignoring mode %dx%d\n",
- mode->hdisplay, mode->vdisplay);
-
- return MODE_BAD;
-}
-
-static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *orig_mode,
- struct drm_display_mode *mode)
-{
- struct imx_tve *tve = enc_to_tve(encoder);
- unsigned long rounded_rate;
- unsigned long rate;
- int div = 1;
- int ret;
-
- /*
- * FIXME
- * we should try 4k * mode->clock first,
- * and enable 4x oversampling for lower resolutions
- */
- rate = 2000UL * mode->clock;
- clk_set_rate(tve->clk, rate);
- rounded_rate = clk_get_rate(tve->clk);
- if (rounded_rate >= rate)
- div = 2;
- clk_set_rate(tve->di_clk, rounded_rate / div);
-
- ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
- if (ret < 0) {
- dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
- ret);
- }
-
- regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
- TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
-
- if (tve->mode == TVE_MODE_VGA)
- ret = tve_setup_vga(tve);
- else
- ret = tve_setup_tvout(tve);
- if (ret)
- dev_err(tve->dev, "failed to set configuration: %d\n", ret);
-}
-
-static void imx_tve_encoder_enable(struct drm_encoder *encoder)
-{
- struct imx_tve *tve = enc_to_tve(encoder);
-
- tve_enable(tve);
-}
-
-static void imx_tve_encoder_disable(struct drm_encoder *encoder)
-{
- struct imx_tve *tve = enc_to_tve(encoder);
-
- tve_disable(tve);
-}
-
-static int imx_tve_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
- struct imx_tve *tve = enc_to_tve(encoder);
-
- imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
- imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
- imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
-
- return 0;
-}
-
-static const struct drm_connector_funcs imx_tve_connector_funcs = {
- .fill_modes = drm_helper_probe_single_connector_modes,
- .destroy = imx_drm_connector_destroy,
- .reset = drm_atomic_helper_connector_reset,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
- .get_modes = imx_tve_connector_get_modes,
- .mode_valid = imx_tve_connector_mode_valid,
-};
-
-static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
- .mode_set = imx_tve_encoder_mode_set,
- .enable = imx_tve_encoder_enable,
- .disable = imx_tve_encoder_disable,
- .atomic_check = imx_tve_atomic_check,
-};
-
-static irqreturn_t imx_tve_irq_handler(int irq, void *data)
-{
- struct imx_tve *tve = data;
- unsigned int val;
-
- regmap_read(tve->regmap, TVE_STAT_REG, &val);
-
- /* clear interrupt status register */
- regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
-
- return IRQ_HANDLED;
-}
-
-static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
- unsigned int val;
- int ret;
-
- ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
- if (ret < 0)
- return 0;
-
- switch (val & TVE_DAC_SAMP_RATE_MASK) {
- case TVE_DAC_DIV4_RATE:
- return parent_rate / 4;
- case TVE_DAC_DIV2_RATE:
- return parent_rate / 2;
- case TVE_DAC_FULL_RATE:
- default:
- return parent_rate;
- }
-
- return 0;
-}
-
-static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
-{
- unsigned long div;
-
- div = *prate / rate;
- if (div >= 4)
- return *prate / 4;
- else if (div >= 2)
- return *prate / 2;
- return *prate;
-}
-
-static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
- unsigned long div;
- u32 val;
- int ret;
-
- div = parent_rate / rate;
- if (div >= 4)
- val = TVE_DAC_DIV4_RATE;
- else if (div >= 2)
- val = TVE_DAC_DIV2_RATE;
- else
- val = TVE_DAC_FULL_RATE;
-
- ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
- TVE_DAC_SAMP_RATE_MASK, val);
-
- if (ret < 0) {
- dev_err(tve->dev, "failed to set divider: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-static const struct clk_ops clk_tve_di_ops = {
- .round_rate = clk_tve_di_round_rate,
- .set_rate = clk_tve_di_set_rate,
- .recalc_rate = clk_tve_di_recalc_rate,
-};
-
-static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
-{
- const char *tve_di_parent[1];
- struct clk_init_data init = {
- .name = "tve_di",
- .ops = &clk_tve_di_ops,
- .num_parents = 1,
- .flags = 0,
- };
-
- tve_di_parent[0] = __clk_get_name(tve->clk);
- init.parent_names = (const char **)&tve_di_parent;
-
- tve->clk_hw_di.init = &init;
- tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di);
- if (IS_ERR(tve->di_clk)) {
- dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
- PTR_ERR(tve->di_clk));
- return PTR_ERR(tve->di_clk);
- }
-
- return 0;
-}
-
-static void imx_tve_disable_regulator(void *data)
-{
- struct imx_tve *tve = data;
-
- regulator_disable(tve->dac_reg);
-}
-
-static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
-{
- return (reg % 4 == 0) && (reg <= 0xdc);
-}
-
-static struct regmap_config tve_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
-
- .readable_reg = imx_tve_readable_reg,
-
- .fast_io = true,
-
- .max_register = 0xdc,
-};
-
-static const char * const imx_tve_modes[] = {
- [TVE_MODE_TVOUT] = "tvout",
- [TVE_MODE_VGA] = "vga",
-};
-
-static int of_get_tve_mode(struct device_node *np)
-{
- const char *bm;
- int ret, i;
-
- ret = of_property_read_string(np, "fsl,tve-mode", &bm);
- if (ret < 0)
- return ret;
-
- for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
- if (!strcasecmp(bm, imx_tve_modes[i]))
- return i;
-
- return -EINVAL;
-}
-
-static int imx_tve_bind(struct device *dev, struct device *master, void *data)
-{
- struct drm_device *drm = data;
- struct imx_tve *tve = dev_get_drvdata(dev);
- struct imx_tve_encoder *tvee;
- struct drm_encoder *encoder;
- struct drm_connector *connector;
- int encoder_type;
- int ret;
-
- encoder_type = tve->mode == TVE_MODE_VGA ?
- DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
-
- tvee = drmm_simple_encoder_alloc(drm, struct imx_tve_encoder, encoder,
- encoder_type);
- if (IS_ERR(tvee))
- return PTR_ERR(tvee);
-
- tvee->tve = tve;
- encoder = &tvee->encoder;
- connector = &tvee->connector;
-
- ret = imx_drm_encoder_parse_of(drm, encoder, tve->dev->of_node);
- if (ret)
- return ret;
-
- drm_encoder_helper_add(encoder, &imx_tve_encoder_helper_funcs);
-
- drm_connector_helper_add(connector, &imx_tve_connector_helper_funcs);
- ret = drm_connector_init_with_ddc(drm, connector,
- &imx_tve_connector_funcs,
- DRM_MODE_CONNECTOR_VGA, tve->ddc);
- if (ret)
- return ret;
-
- return drm_connector_attach_encoder(connector, encoder);
-}
-
-static const struct component_ops imx_tve_ops = {
- .bind = imx_tve_bind,
-};
-
-static int imx_tve_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct device_node *ddc_node;
- struct imx_tve *tve;
- void __iomem *base;
- unsigned int val;
- int irq;
- int ret;
-
- tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
- if (!tve)
- return -ENOMEM;
-
- tve->dev = dev;
-
- ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
- if (ddc_node) {
- tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
- of_node_put(ddc_node);
- }
-
- tve->mode = of_get_tve_mode(np);
- if (tve->mode != TVE_MODE_VGA) {
- dev_err(dev, "only VGA mode supported, currently\n");
- return -EINVAL;
- }
-
- if (tve->mode == TVE_MODE_VGA) {
- ret = of_property_read_u32(np, "fsl,hsync-pin",
- &tve->di_hsync_pin);
-
- if (ret < 0) {
- dev_err(dev, "failed to get hsync pin\n");
- return ret;
- }
-
- ret = of_property_read_u32(np, "fsl,vsync-pin",
- &tve->di_vsync_pin);
-
- if (ret < 0) {
- dev_err(dev, "failed to get vsync pin\n");
- return ret;
- }
- }
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- tve_regmap_config.lock_arg = tve;
- tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
- &tve_regmap_config);
- if (IS_ERR(tve->regmap)) {
- dev_err(dev, "failed to init regmap: %ld\n",
- PTR_ERR(tve->regmap));
- return PTR_ERR(tve->regmap);
- }
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- ret = devm_request_threaded_irq(dev, irq, NULL,
- imx_tve_irq_handler, IRQF_ONESHOT,
- "imx-tve", tve);
- if (ret < 0) {
- dev_err(dev, "failed to request irq: %d\n", ret);
- return ret;
- }
-
- tve->dac_reg = devm_regulator_get(dev, "dac");
- if (!IS_ERR(tve->dac_reg)) {
- if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
- dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
- ret = regulator_enable(tve->dac_reg);
- if (ret)
- return ret;
- ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
- if (ret)
- return ret;
- }
-
- tve->clk = devm_clk_get(dev, "tve");
- if (IS_ERR(tve->clk)) {
- dev_err(dev, "failed to get high speed tve clock: %ld\n",
- PTR_ERR(tve->clk));
- return PTR_ERR(tve->clk);
- }
-
- /* this is the IPU DI clock input selector, can be parented to tve_di */
- tve->di_sel_clk = devm_clk_get(dev, "di_sel");
- if (IS_ERR(tve->di_sel_clk)) {
- dev_err(dev, "failed to get ipu di mux clock: %ld\n",
- PTR_ERR(tve->di_sel_clk));
- return PTR_ERR(tve->di_sel_clk);
- }
-
- ret = tve_clk_init(tve, base);
- if (ret < 0)
- return ret;
-
- ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
- if (ret < 0) {
- dev_err(dev, "failed to read configuration register: %d\n",
- ret);
- return ret;
- }
- if (val != 0x00100000) {
- dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
- return -ENODEV;
- }
-
- /* disable cable detection for VGA mode */
- ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
- if (ret)
- return ret;
-
- platform_set_drvdata(pdev, tve);
-
- return component_add(dev, &imx_tve_ops);
-}
-
-static int imx_tve_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &imx_tve_ops);
- return 0;
-}
-
-static const struct of_device_id imx_tve_dt_ids[] = {
- { .compatible = "fsl,imx53-tve", },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
-
-static struct platform_driver imx_tve_driver = {
- .probe = imx_tve_probe,
- .remove = imx_tve_remove,
- .driver = {
- .of_match_table = imx_tve_dt_ids,
- .name = "imx-tve",
- },
-};
-
-module_platform_driver(imx_tve_driver);
-
-MODULE_DESCRIPTION("i.MX Television Encoder driver");
-MODULE_AUTHOR("Philipp Zabel, Pengutronix");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:imx-tve");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * i.MX IPUv3 Graphics driver
- *
- * Copyright (C) 2011 Sascha Hauer, Pengutronix
- */
-
-#include <linux/clk.h>
-#include <linux/component.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/errno.h>
-#include <linux/export.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-
-#include <video/imx-ipu-v3.h>
-
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_gem_dma_helper.h>
-#include <drm/drm_managed.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_vblank.h>
-
-#include "imx-drm.h"
-#include "ipuv3-plane.h"
-
-#define DRIVER_DESC "i.MX IPUv3 Graphics"
-
-struct ipu_crtc {
- struct device *dev;
- struct drm_crtc base;
-
- /* plane[0] is the full plane, plane[1] is the partial plane */
- struct ipu_plane *plane[2];
-
- struct ipu_dc *dc;
- struct ipu_di *di;
- int irq;
- struct drm_pending_vblank_event *event;
-};
-
-static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
-{
- return container_of(crtc, struct ipu_crtc, base);
-}
-
-static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
- struct drm_atomic_state *state)
-{
- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
- struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
-
- ipu_prg_enable(ipu);
- ipu_dc_enable(ipu);
- ipu_dc_enable_channel(ipu_crtc->dc);
- ipu_di_enable(ipu_crtc->di);
-}
-
-static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
- struct drm_crtc_state *old_crtc_state)
-{
- bool disable_partial = false;
- bool disable_full = false;
- struct drm_plane *plane;
-
- drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
- if (plane == &ipu_crtc->plane[0]->base)
- disable_full = true;
- if (ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
- disable_partial = true;
- }
-
- if (disable_partial)
- ipu_plane_disable(ipu_crtc->plane[1], true);
- if (disable_full)
- ipu_plane_disable(ipu_crtc->plane[0], true);
-}
-
-static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
- struct drm_atomic_state *state)
-{
- struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
- crtc);
- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
- struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
-
- ipu_dc_disable_channel(ipu_crtc->dc);
- ipu_di_disable(ipu_crtc->di);
- /*
- * Planes must be disabled before DC clock is removed, as otherwise the
- * attached IDMACs will be left in undefined state, possibly hanging
- * the IPU or even system.
- */
- ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
- ipu_dc_disable(ipu);
- ipu_prg_disable(ipu);
-
- drm_crtc_vblank_off(crtc);
-
- spin_lock_irq(&crtc->dev->event_lock);
- if (crtc->state->event && !crtc->state->active) {
- drm_crtc_send_vblank_event(crtc, crtc->state->event);
- crtc->state->event = NULL;
- }
- spin_unlock_irq(&crtc->dev->event_lock);
-}
-
-static void imx_drm_crtc_reset(struct drm_crtc *crtc)
-{
- struct imx_crtc_state *state;
-
- if (crtc->state)
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
-
- kfree(to_imx_crtc_state(crtc->state));
- crtc->state = NULL;
-
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (state)
- __drm_atomic_helper_crtc_reset(crtc, &state->base);
-}
-
-static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
-{
- struct imx_crtc_state *state;
-
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (!state)
- return NULL;
-
- __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
-
- WARN_ON(state->base.crtc != crtc);
- state->base.crtc = crtc;
-
- return &state->base;
-}
-
-static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
- struct drm_crtc_state *state)
-{
- __drm_atomic_helper_crtc_destroy_state(state);
- kfree(to_imx_crtc_state(state));
-}
-
-static int ipu_enable_vblank(struct drm_crtc *crtc)
-{
- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
-
- enable_irq(ipu_crtc->irq);
-
- return 0;
-}
-
-static void ipu_disable_vblank(struct drm_crtc *crtc)
-{
- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
-
- disable_irq_nosync(ipu_crtc->irq);
-}
-
-static const struct drm_crtc_funcs ipu_crtc_funcs = {
- .set_config = drm_atomic_helper_set_config,
- .page_flip = drm_atomic_helper_page_flip,
- .reset = imx_drm_crtc_reset,
- .atomic_duplicate_state = imx_drm_crtc_duplicate_state,
- .atomic_destroy_state = imx_drm_crtc_destroy_state,
- .enable_vblank = ipu_enable_vblank,
- .disable_vblank = ipu_disable_vblank,
-};
-
-static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
-{
- struct ipu_crtc *ipu_crtc = dev_id;
- struct drm_crtc *crtc = &ipu_crtc->base;
- unsigned long flags;
- int i;
-
- drm_crtc_handle_vblank(crtc);
-
- if (ipu_crtc->event) {
- for (i = 0; i < ARRAY_SIZE(ipu_crtc->plane); i++) {
- struct ipu_plane *plane = ipu_crtc->plane[i];
-
- if (!plane)
- continue;
-
- if (ipu_plane_atomic_update_pending(&plane->base))
- break;
- }
-
- if (i == ARRAY_SIZE(ipu_crtc->plane)) {
- spin_lock_irqsave(&crtc->dev->event_lock, flags);
- drm_crtc_send_vblank_event(crtc, ipu_crtc->event);
- ipu_crtc->event = NULL;
- drm_crtc_vblank_put(crtc);
- spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
- }
- }
-
- return IRQ_HANDLED;
-}
-
-static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
- struct videomode vm;
- int ret;
-
- drm_display_mode_to_videomode(adjusted_mode, &vm);
-
- ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
- if (ret)
- return false;
-
- if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
- return false;
-
- drm_display_mode_from_videomode(&vm, adjusted_mode);
-
- return true;
-}
-
-static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
- struct drm_atomic_state *state)
-{
- struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
- crtc);
- u32 primary_plane_mask = drm_plane_mask(crtc->primary);
-
- if (crtc_state->active && (primary_plane_mask & crtc_state->plane_mask) == 0)
- return -EINVAL;
-
- return 0;
-}
-
-static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
- struct drm_atomic_state *state)
-{
- drm_crtc_vblank_on(crtc);
-}
-
-static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
- struct drm_atomic_state *state)
-{
- spin_lock_irq(&crtc->dev->event_lock);
- if (crtc->state->event) {
- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
-
- WARN_ON(drm_crtc_vblank_get(crtc));
- ipu_crtc->event = crtc->state->event;
- crtc->state->event = NULL;
- }
- spin_unlock_irq(&crtc->dev->event_lock);
-}
-
-static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
-{
- struct drm_device *dev = crtc->dev;
- struct drm_encoder *encoder;
- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
- struct drm_display_mode *mode = &crtc->state->adjusted_mode;
- struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
- struct ipu_di_signal_cfg sig_cfg = {};
- unsigned long encoder_types = 0;
-
- dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
- mode->hdisplay);
- dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
- mode->vdisplay);
-
- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
- if (encoder->crtc == crtc)
- encoder_types |= BIT(encoder->encoder_type);
- }
-
- dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
- __func__, encoder_types);
-
- /*
- * If we have DAC or LDB, then we need the IPU DI clock to be
- * the same as the LDB DI clock. For TVDAC, derive the IPU DI
- * clock from 27 MHz TVE_DI clock, but allow to divide it.
- */
- if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
- BIT(DRM_MODE_ENCODER_LVDS)))
- sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
- else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
- sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
- else
- sig_cfg.clkflags = 0;
-
- sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
- /* Default to driving pixel data on negative clock edges */
- sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
- DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE);
- sig_cfg.bus_format = imx_crtc_state->bus_format;
- sig_cfg.v_to_h_sync = 0;
- sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
- sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
-
- drm_display_mode_to_videomode(mode, &sig_cfg.mode);
- if (!IS_ALIGNED(sig_cfg.mode.hactive, 8)) {
- unsigned int new_hactive = ALIGN(sig_cfg.mode.hactive, 8);
-
- dev_warn(ipu_crtc->dev, "8-pixel align hactive %d -> %d\n",
- sig_cfg.mode.hactive, new_hactive);
-
- sig_cfg.mode.hfront_porch = new_hactive - sig_cfg.mode.hactive;
- sig_cfg.mode.hactive = new_hactive;
- }
-
- ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
- mode->flags & DRM_MODE_FLAG_INTERLACE,
- imx_crtc_state->bus_format, sig_cfg.mode.hactive);
- ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
-}
-
-static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
- .mode_fixup = ipu_crtc_mode_fixup,
- .mode_set_nofb = ipu_crtc_mode_set_nofb,
- .atomic_check = ipu_crtc_atomic_check,
- .atomic_begin = ipu_crtc_atomic_begin,
- .atomic_flush = ipu_crtc_atomic_flush,
- .atomic_disable = ipu_crtc_atomic_disable,
- .atomic_enable = ipu_crtc_atomic_enable,
-};
-
-static void ipu_put_resources(struct drm_device *dev, void *ptr)
-{
- struct ipu_crtc *ipu_crtc = ptr;
-
- if (!IS_ERR_OR_NULL(ipu_crtc->dc))
- ipu_dc_put(ipu_crtc->dc);
- if (!IS_ERR_OR_NULL(ipu_crtc->di))
- ipu_di_put(ipu_crtc->di);
-}
-
-static int ipu_get_resources(struct drm_device *dev, struct ipu_crtc *ipu_crtc,
- struct ipu_client_platformdata *pdata)
-{
- struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
- int ret;
-
- ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
- if (IS_ERR(ipu_crtc->dc))
- return PTR_ERR(ipu_crtc->dc);
-
- ret = drmm_add_action_or_reset(dev, ipu_put_resources, ipu_crtc);
- if (ret)
- return ret;
-
- ipu_crtc->di = ipu_di_get(ipu, pdata->di);
- if (IS_ERR(ipu_crtc->di))
- return PTR_ERR(ipu_crtc->di);
-
- return 0;
-}
-
-static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
-{
- struct ipu_client_platformdata *pdata = dev->platform_data;
- struct ipu_soc *ipu = dev_get_drvdata(dev->parent);
- struct drm_device *drm = data;
- struct ipu_plane *primary_plane;
- struct ipu_crtc *ipu_crtc;
- struct drm_crtc *crtc;
- int dp = -EINVAL;
- int ret;
-
- if (pdata->dp >= 0)
- dp = IPU_DP_FLOW_SYNC_BG;
- primary_plane = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
- DRM_PLANE_TYPE_PRIMARY);
- if (IS_ERR(primary_plane))
- return PTR_ERR(primary_plane);
-
- ipu_crtc = drmm_crtc_alloc_with_planes(drm, struct ipu_crtc, base,
- &primary_plane->base, NULL,
- &ipu_crtc_funcs, NULL);
- if (IS_ERR(ipu_crtc))
- return PTR_ERR(ipu_crtc);
-
- ipu_crtc->dev = dev;
- ipu_crtc->plane[0] = primary_plane;
-
- crtc = &ipu_crtc->base;
- crtc->port = pdata->of_node;
- drm_crtc_helper_add(crtc, &ipu_helper_funcs);
-
- ret = ipu_get_resources(drm, ipu_crtc, pdata);
- if (ret) {
- dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
- ret);
- return ret;
- }
-
- /* If this crtc is using the DP, add an overlay plane */
- if (pdata->dp >= 0 && pdata->dma[1] > 0) {
- ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
- IPU_DP_FLOW_SYNC_FG,
- drm_crtc_mask(&ipu_crtc->base),
- DRM_PLANE_TYPE_OVERLAY);
- if (IS_ERR(ipu_crtc->plane[1]))
- ipu_crtc->plane[1] = NULL;
- }
-
- ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
- ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
- "imx_drm", ipu_crtc);
- if (ret < 0) {
- dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
- return ret;
- }
- /* Only enable IRQ when we actually need it to trigger work. */
- disable_irq(ipu_crtc->irq);
-
- return 0;
-}
-
-static const struct component_ops ipu_crtc_ops = {
- .bind = ipu_drm_bind,
-};
-
-static int ipu_drm_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- int ret;
-
- if (!dev->platform_data)
- return -EINVAL;
-
- ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
- if (ret)
- return ret;
-
- return component_add(dev, &ipu_crtc_ops);
-}
-
-static int ipu_drm_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &ipu_crtc_ops);
- return 0;
-}
-
-struct platform_driver ipu_drm_driver = {
- .driver = {
- .name = "imx-ipuv3-crtc",
- },
- .probe = ipu_drm_probe,
- .remove = ipu_drm_remove,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * i.MX IPUv3 DP Overlay Planes
- *
- * Copyright (C) 2013 Philipp Zabel, Pengutronix
- */
-
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_blend.h>
-#include <drm/drm_fb_dma_helper.h>
-#include <drm/drm_fourcc.h>
-#include <drm/drm_framebuffer.h>
-#include <drm/drm_gem_atomic_helper.h>
-#include <drm/drm_gem_dma_helper.h>
-#include <drm/drm_managed.h>
-
-#include <video/imx-ipu-v3.h>
-
-#include "imx-drm.h"
-#include "ipuv3-plane.h"
-
-struct ipu_plane_state {
- struct drm_plane_state base;
- bool use_pre;
-};
-
-static inline struct ipu_plane_state *
-to_ipu_plane_state(struct drm_plane_state *p)
-{
- return container_of(p, struct ipu_plane_state, base);
-}
-
-static unsigned int ipu_src_rect_width(const struct drm_plane_state *state)
-{
- return ALIGN(drm_rect_width(&state->src) >> 16, 8);
-}
-
-static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
-{
- return container_of(p, struct ipu_plane, base);
-}
-
-static const uint32_t ipu_plane_all_formats[] = {
- DRM_FORMAT_ARGB1555,
- DRM_FORMAT_XRGB1555,
- DRM_FORMAT_ABGR1555,
- DRM_FORMAT_XBGR1555,
- DRM_FORMAT_RGBA5551,
- DRM_FORMAT_BGRA5551,
- DRM_FORMAT_ARGB4444,
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_XBGR8888,
- DRM_FORMAT_RGBA8888,
- DRM_FORMAT_RGBX8888,
- DRM_FORMAT_BGRA8888,
- DRM_FORMAT_BGRX8888,
- DRM_FORMAT_UYVY,
- DRM_FORMAT_VYUY,
- DRM_FORMAT_YUYV,
- DRM_FORMAT_YVYU,
- DRM_FORMAT_YUV420,
- DRM_FORMAT_YVU420,
- DRM_FORMAT_YUV422,
- DRM_FORMAT_YVU422,
- DRM_FORMAT_YUV444,
- DRM_FORMAT_YVU444,
- DRM_FORMAT_NV12,
- DRM_FORMAT_NV16,
- DRM_FORMAT_RGB565,
- DRM_FORMAT_RGB565_A8,
- DRM_FORMAT_BGR565_A8,
- DRM_FORMAT_RGB888_A8,
- DRM_FORMAT_BGR888_A8,
- DRM_FORMAT_RGBX8888_A8,
- DRM_FORMAT_BGRX8888_A8,
-};
-
-static const uint32_t ipu_plane_rgb_formats[] = {
- DRM_FORMAT_ARGB1555,
- DRM_FORMAT_XRGB1555,
- DRM_FORMAT_ABGR1555,
- DRM_FORMAT_XBGR1555,
- DRM_FORMAT_RGBA5551,
- DRM_FORMAT_BGRA5551,
- DRM_FORMAT_ARGB4444,
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_XBGR8888,
- DRM_FORMAT_RGBA8888,
- DRM_FORMAT_RGBX8888,
- DRM_FORMAT_BGRA8888,
- DRM_FORMAT_BGRX8888,
- DRM_FORMAT_RGB565,
- DRM_FORMAT_RGB565_A8,
- DRM_FORMAT_BGR565_A8,
- DRM_FORMAT_RGB888_A8,
- DRM_FORMAT_BGR888_A8,
- DRM_FORMAT_RGBX8888_A8,
- DRM_FORMAT_BGRX8888_A8,
-};
-
-static const uint64_t ipu_format_modifiers[] = {
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const uint64_t pre_format_modifiers[] = {
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_VIVANTE_TILED,
- DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
- DRM_FORMAT_MOD_INVALID
-};
-
-int ipu_plane_irq(struct ipu_plane *ipu_plane)
-{
- return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
- IPU_IRQ_EOF);
-}
-
-static inline unsigned long
-drm_plane_state_to_eba(struct drm_plane_state *state, int plane)
-{
- struct drm_framebuffer *fb = state->fb;
- struct drm_gem_dma_object *dma_obj;
- int x = state->src.x1 >> 16;
- int y = state->src.y1 >> 16;
-
- dma_obj = drm_fb_dma_get_gem_obj(fb, plane);
- BUG_ON(!dma_obj);
-
- return dma_obj->dma_addr + fb->offsets[plane] + fb->pitches[plane] * y +
- fb->format->cpp[plane] * x;
-}
-
-static inline unsigned long
-drm_plane_state_to_ubo(struct drm_plane_state *state)
-{
- struct drm_framebuffer *fb = state->fb;
- struct drm_gem_dma_object *dma_obj;
- unsigned long eba = drm_plane_state_to_eba(state, 0);
- int x = state->src.x1 >> 16;
- int y = state->src.y1 >> 16;
-
- dma_obj = drm_fb_dma_get_gem_obj(fb, 1);
- BUG_ON(!dma_obj);
-
- x /= fb->format->hsub;
- y /= fb->format->vsub;
-
- return dma_obj->dma_addr + fb->offsets[1] + fb->pitches[1] * y +
- fb->format->cpp[1] * x - eba;
-}
-
-static inline unsigned long
-drm_plane_state_to_vbo(struct drm_plane_state *state)
-{
- struct drm_framebuffer *fb = state->fb;
- struct drm_gem_dma_object *dma_obj;
- unsigned long eba = drm_plane_state_to_eba(state, 0);
- int x = state->src.x1 >> 16;
- int y = state->src.y1 >> 16;
-
- dma_obj = drm_fb_dma_get_gem_obj(fb, 2);
- BUG_ON(!dma_obj);
-
- x /= fb->format->hsub;
- y /= fb->format->vsub;
-
- return dma_obj->dma_addr + fb->offsets[2] + fb->pitches[2] * y +
- fb->format->cpp[2] * x - eba;
-}
-
-static void ipu_plane_put_resources(struct drm_device *dev, void *ptr)
-{
- struct ipu_plane *ipu_plane = ptr;
-
- if (!IS_ERR_OR_NULL(ipu_plane->dp))
- ipu_dp_put(ipu_plane->dp);
- if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
- ipu_dmfc_put(ipu_plane->dmfc);
- if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
- ipu_idmac_put(ipu_plane->ipu_ch);
- if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch))
- ipu_idmac_put(ipu_plane->alpha_ch);
-}
-
-static int ipu_plane_get_resources(struct drm_device *dev,
- struct ipu_plane *ipu_plane)
-{
- int ret;
- int alpha_ch;
-
- ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
- if (IS_ERR(ipu_plane->ipu_ch)) {
- ret = PTR_ERR(ipu_plane->ipu_ch);
- DRM_ERROR("failed to get idmac channel: %d\n", ret);
- return ret;
- }
-
- ret = drmm_add_action_or_reset(dev, ipu_plane_put_resources, ipu_plane);
- if (ret)
- return ret;
-
- alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma);
- if (alpha_ch >= 0) {
- ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch);
- if (IS_ERR(ipu_plane->alpha_ch)) {
- ret = PTR_ERR(ipu_plane->alpha_ch);
- DRM_ERROR("failed to get alpha idmac channel %d: %d\n",
- alpha_ch, ret);
- return ret;
- }
- }
-
- ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
- if (IS_ERR(ipu_plane->dmfc)) {
- ret = PTR_ERR(ipu_plane->dmfc);
- DRM_ERROR("failed to get dmfc: ret %d\n", ret);
- return ret;
- }
-
- if (ipu_plane->dp_flow >= 0) {
- ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
- if (IS_ERR(ipu_plane->dp)) {
- ret = PTR_ERR(ipu_plane->dp);
- DRM_ERROR("failed to get dp flow: %d\n", ret);
- return ret;
- }
- }
-
- return 0;
-}
-
-static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane)
-{
- switch (ipu_plane->base.state->fb->format->format) {
- case DRM_FORMAT_RGB565_A8:
- case DRM_FORMAT_BGR565_A8:
- case DRM_FORMAT_RGB888_A8:
- case DRM_FORMAT_BGR888_A8:
- case DRM_FORMAT_RGBX8888_A8:
- case DRM_FORMAT_BGRX8888_A8:
- return true;
- default:
- return false;
- }
-}
-
-static void ipu_plane_enable(struct ipu_plane *ipu_plane)
-{
- if (ipu_plane->dp)
- ipu_dp_enable(ipu_plane->ipu);
- ipu_dmfc_enable_channel(ipu_plane->dmfc);
- ipu_idmac_enable_channel(ipu_plane->ipu_ch);
- if (ipu_plane_separate_alpha(ipu_plane))
- ipu_idmac_enable_channel(ipu_plane->alpha_ch);
- if (ipu_plane->dp)
- ipu_dp_enable_channel(ipu_plane->dp);
-}
-
-void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel)
-{
- int ret;
-
- DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
-
- ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
- if (ret == -ETIMEDOUT) {
- DRM_ERROR("[PLANE:%d] IDMAC timeout\n",
- ipu_plane->base.base.id);
- }
-
- if (ipu_plane->dp && disable_dp_channel)
- ipu_dp_disable_channel(ipu_plane->dp, false);
- ipu_idmac_disable_channel(ipu_plane->ipu_ch);
- if (ipu_plane->alpha_ch)
- ipu_idmac_disable_channel(ipu_plane->alpha_ch);
- ipu_dmfc_disable_channel(ipu_plane->dmfc);
- if (ipu_plane->dp)
- ipu_dp_disable(ipu_plane->ipu);
- if (ipu_prg_present(ipu_plane->ipu))
- ipu_prg_channel_disable(ipu_plane->ipu_ch);
-}
-
-void ipu_plane_disable_deferred(struct drm_plane *plane)
-{
- struct ipu_plane *ipu_plane = to_ipu_plane(plane);
-
- if (ipu_plane->disabling) {
- ipu_plane->disabling = false;
- ipu_plane_disable(ipu_plane, false);
- }
-}
-
-static void ipu_plane_state_reset(struct drm_plane *plane)
-{
- struct ipu_plane_state *ipu_state;
-
- if (plane->state) {
- ipu_state = to_ipu_plane_state(plane->state);
- __drm_atomic_helper_plane_destroy_state(plane->state);
- kfree(ipu_state);
- plane->state = NULL;
- }
-
- ipu_state = kzalloc(sizeof(*ipu_state), GFP_KERNEL);
-
- if (ipu_state)
- __drm_atomic_helper_plane_reset(plane, &ipu_state->base);
-}
-
-static struct drm_plane_state *
-ipu_plane_duplicate_state(struct drm_plane *plane)
-{
- struct ipu_plane_state *state;
-
- if (WARN_ON(!plane->state))
- return NULL;
-
- state = kmalloc(sizeof(*state), GFP_KERNEL);
- if (state)
- __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
-
- return &state->base;
-}
-
-static void ipu_plane_destroy_state(struct drm_plane *plane,
- struct drm_plane_state *state)
-{
- struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
-
- __drm_atomic_helper_plane_destroy_state(state);
- kfree(ipu_state);
-}
-
-static bool ipu_plane_format_mod_supported(struct drm_plane *plane,
- uint32_t format, uint64_t modifier)
-{
- struct ipu_soc *ipu = to_ipu_plane(plane)->ipu;
-
- /* linear is supported for all planes and formats */
- if (modifier == DRM_FORMAT_MOD_LINEAR)
- return true;
-
- /*
- * Without a PRG the possible modifiers list only includes the linear
- * modifier, so we always take the early return from this function and
- * only end up here if the PRG is present.
- */
- return ipu_prg_format_supported(ipu, format, modifier);
-}
-
-static const struct drm_plane_funcs ipu_plane_funcs = {
- .update_plane = drm_atomic_helper_update_plane,
- .disable_plane = drm_atomic_helper_disable_plane,
- .reset = ipu_plane_state_reset,
- .atomic_duplicate_state = ipu_plane_duplicate_state,
- .atomic_destroy_state = ipu_plane_destroy_state,
- .format_mod_supported = ipu_plane_format_mod_supported,
-};
-
-static int ipu_plane_atomic_check(struct drm_plane *plane,
- struct drm_atomic_state *state)
-{
- struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
- plane);
- struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
- plane);
- struct drm_crtc_state *crtc_state;
- struct device *dev = plane->dev->dev;
- struct drm_framebuffer *fb = new_state->fb;
- struct drm_framebuffer *old_fb = old_state->fb;
- unsigned long eba, ubo, vbo, old_ubo, old_vbo, alpha_eba;
- bool can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
- int ret;
-
- /* Ok to disable */
- if (!fb)
- return 0;
-
- if (WARN_ON(!new_state->crtc))
- return -EINVAL;
-
- crtc_state =
- drm_atomic_get_existing_crtc_state(state,
- new_state->crtc);
- if (WARN_ON(!crtc_state))
- return -EINVAL;
-
- ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,
- DRM_PLANE_NO_SCALING,
- DRM_PLANE_NO_SCALING,
- can_position, true);
- if (ret)
- return ret;
-
- /* nothing to check when disabling or disabled */
- if (!crtc_state->enable)
- return 0;
-
- switch (plane->type) {
- case DRM_PLANE_TYPE_PRIMARY:
- /* full plane minimum width is 13 pixels */
- if (drm_rect_width(&new_state->dst) < 13)
- return -EINVAL;
- break;
- case DRM_PLANE_TYPE_OVERLAY:
- break;
- default:
- dev_warn(dev, "Unsupported plane type %d\n", plane->type);
- return -EINVAL;
- }
-
- if (drm_rect_height(&new_state->dst) < 2)
- return -EINVAL;
-
- /*
- * We support resizing active plane or changing its format by
- * forcing CRTC mode change in plane's ->atomic_check callback
- * and disabling all affected active planes in CRTC's ->atomic_disable
- * callback. The planes will be reenabled in plane's ->atomic_update
- * callback.
- */
- if (old_fb &&
- (drm_rect_width(&new_state->dst) != drm_rect_width(&old_state->dst) ||
- drm_rect_height(&new_state->dst) != drm_rect_height(&old_state->dst) ||
- fb->format != old_fb->format))
- crtc_state->mode_changed = true;
-
- eba = drm_plane_state_to_eba(new_state, 0);
-
- if (eba & 0x7)
- return -EINVAL;
-
- if (fb->pitches[0] < 1 || fb->pitches[0] > 16384)
- return -EINVAL;
-
- if (old_fb && fb->pitches[0] != old_fb->pitches[0])
- crtc_state->mode_changed = true;
-
- if (ALIGN(fb->width, 8) * fb->format->cpp[0] >
- fb->pitches[0] + fb->offsets[0]) {
- dev_warn(dev, "pitch is not big enough for 8 pixels alignment");
- return -EINVAL;
- }
-
- switch (fb->format->format) {
- case DRM_FORMAT_YUV420:
- case DRM_FORMAT_YVU420:
- case DRM_FORMAT_YUV422:
- case DRM_FORMAT_YVU422:
- case DRM_FORMAT_YUV444:
- case DRM_FORMAT_YVU444:
- /*
- * Multiplanar formats have to meet the following restrictions:
- * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
- * - EBA, UBO and VBO are a multiple of 8
- * - UBO and VBO are unsigned and not larger than 0xfffff8
- * - Only EBA may be changed while scanout is active
- * - The strides of U and V planes must be identical.
- */
- vbo = drm_plane_state_to_vbo(new_state);
-
- if (vbo & 0x7 || vbo > 0xfffff8)
- return -EINVAL;
-
- if (old_fb && (fb->format == old_fb->format)) {
- old_vbo = drm_plane_state_to_vbo(old_state);
- if (vbo != old_vbo)
- crtc_state->mode_changed = true;
- }
-
- if (fb->pitches[1] != fb->pitches[2])
- return -EINVAL;
-
- fallthrough;
- case DRM_FORMAT_NV12:
- case DRM_FORMAT_NV16:
- ubo = drm_plane_state_to_ubo(new_state);
-
- if (ubo & 0x7 || ubo > 0xfffff8)
- return -EINVAL;
-
- if (old_fb && (fb->format == old_fb->format)) {
- old_ubo = drm_plane_state_to_ubo(old_state);
- if (ubo != old_ubo)
- crtc_state->mode_changed = true;
- }
-
- if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
- return -EINVAL;
-
- if (old_fb && old_fb->pitches[1] != fb->pitches[1])
- crtc_state->mode_changed = true;
-
- /*
- * The x/y offsets must be even in case of horizontal/vertical
- * chroma subsampling.
- */
- if (((new_state->src.x1 >> 16) & (fb->format->hsub - 1)) ||
- ((new_state->src.y1 >> 16) & (fb->format->vsub - 1)))
- return -EINVAL;
- break;
- case DRM_FORMAT_RGB565_A8:
- case DRM_FORMAT_BGR565_A8:
- case DRM_FORMAT_RGB888_A8:
- case DRM_FORMAT_BGR888_A8:
- case DRM_FORMAT_RGBX8888_A8:
- case DRM_FORMAT_BGRX8888_A8:
- alpha_eba = drm_plane_state_to_eba(new_state, 1);
- if (alpha_eba & 0x7)
- return -EINVAL;
-
- if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
- return -EINVAL;
-
- if (old_fb && old_fb->pitches[1] != fb->pitches[1])
- crtc_state->mode_changed = true;
- break;
- }
-
- return 0;
-}
-
-static void ipu_plane_atomic_disable(struct drm_plane *plane,
- struct drm_atomic_state *state)
-{
- struct ipu_plane *ipu_plane = to_ipu_plane(plane);
-
- if (ipu_plane->dp)
- ipu_dp_disable_channel(ipu_plane->dp, true);
- ipu_plane->disabling = true;
-}
-
-static int ipu_chan_assign_axi_id(int ipu_chan)
-{
- switch (ipu_chan) {
- case IPUV3_CHANNEL_MEM_BG_SYNC:
- return 1;
- case IPUV3_CHANNEL_MEM_FG_SYNC:
- return 2;
- case IPUV3_CHANNEL_MEM_DC_SYNC:
- return 3;
- default:
- return 0;
- }
-}
-
-static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride,
- u8 *burstsize, u8 *num_bursts)
-{
- const unsigned int width_bytes = width * cpp;
- unsigned int npb, bursts;
-
- /* Maximum number of pixels per burst without overshooting stride */
- for (npb = 64 / cpp; npb > 0; --npb) {
- if (round_up(width_bytes, npb * cpp) <= stride)
- break;
- }
- *burstsize = npb;
-
- /* Maximum number of consecutive bursts without overshooting stride */
- for (bursts = 8; bursts > 1; bursts /= 2) {
- if (round_up(width_bytes, npb * cpp * bursts) <= stride)
- break;
- }
- *num_bursts = bursts;
-}
-
-static void ipu_plane_atomic_update(struct drm_plane *plane,
- struct drm_atomic_state *state)
-{
- struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
- plane);
- struct ipu_plane *ipu_plane = to_ipu_plane(plane);
- struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
- plane);
- struct ipu_plane_state *ipu_state = to_ipu_plane_state(new_state);
- struct drm_crtc_state *crtc_state = new_state->crtc->state;
- struct drm_framebuffer *fb = new_state->fb;
- struct drm_rect *dst = &new_state->dst;
- unsigned long eba, ubo, vbo;
- unsigned long alpha_eba = 0;
- enum ipu_color_space ics;
- unsigned int axi_id = 0;
- const struct drm_format_info *info;
- u8 burstsize, num_bursts;
- u32 width, height;
- int active;
-
- if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG)
- ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1);
-
- switch (ipu_plane->dp_flow) {
- case IPU_DP_FLOW_SYNC_BG:
- if (new_state->normalized_zpos == 1) {
- ipu_dp_set_global_alpha(ipu_plane->dp,
- !fb->format->has_alpha, 0xff,
- true);
- } else {
- ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
- }
- break;
- case IPU_DP_FLOW_SYNC_FG:
- if (new_state->normalized_zpos == 1) {
- ipu_dp_set_global_alpha(ipu_plane->dp,
- !fb->format->has_alpha, 0xff,
- false);
- }
- break;
- }
-
- if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_BG)
- width = ipu_src_rect_width(new_state);
- else
- width = drm_rect_width(&new_state->src) >> 16;
-
- eba = drm_plane_state_to_eba(new_state, 0);
-
- /*
- * Configure PRG channel and attached PRE, this changes the EBA to an
- * internal SRAM location.
- */
- if (ipu_state->use_pre) {
- axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
- ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id, width,
- drm_rect_height(&new_state->src) >> 16,
- fb->pitches[0], fb->format->format,
- fb->modifier, &eba);
- }
-
- if (!old_state->fb ||
- old_state->fb->format->format != fb->format->format ||
- old_state->color_encoding != new_state->color_encoding ||
- old_state->color_range != new_state->color_range) {
- ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
- switch (ipu_plane->dp_flow) {
- case IPU_DP_FLOW_SYNC_BG:
- ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
- new_state->color_range, ics,
- IPUV3_COLORSPACE_RGB);
- break;
- case IPU_DP_FLOW_SYNC_FG:
- ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
- new_state->color_range, ics,
- IPUV3_COLORSPACE_UNKNOWN);
- break;
- }
- }
-
- if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {
- /* nothing to do if PRE is used */
- if (ipu_state->use_pre)
- return;
- active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
- ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
- ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
- if (ipu_plane_separate_alpha(ipu_plane)) {
- active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
- ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
- alpha_eba);
- ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active);
- }
- return;
- }
-
- ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
- switch (ipu_plane->dp_flow) {
- case IPU_DP_FLOW_SYNC_BG:
- ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
- DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
- IPUV3_COLORSPACE_RGB);
- break;
- case IPU_DP_FLOW_SYNC_FG:
- ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
- DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
- IPUV3_COLORSPACE_UNKNOWN);
- break;
- }
-
- ipu_dmfc_config_wait4eot(ipu_plane->dmfc, width);
-
- height = drm_rect_height(&new_state->src) >> 16;
- info = drm_format_info(fb->format->format);
- ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
- &burstsize, &num_bursts);
-
- ipu_cpmem_zero(ipu_plane->ipu_ch);
- ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
- ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
- ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
- ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
- ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
- ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
- ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
- ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
-
- switch (fb->format->format) {
- case DRM_FORMAT_YUV420:
- case DRM_FORMAT_YVU420:
- case DRM_FORMAT_YUV422:
- case DRM_FORMAT_YVU422:
- case DRM_FORMAT_YUV444:
- case DRM_FORMAT_YVU444:
- ubo = drm_plane_state_to_ubo(new_state);
- vbo = drm_plane_state_to_vbo(new_state);
- if (fb->format->format == DRM_FORMAT_YVU420 ||
- fb->format->format == DRM_FORMAT_YVU422 ||
- fb->format->format == DRM_FORMAT_YVU444)
- swap(ubo, vbo);
-
- ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
- fb->pitches[1], ubo, vbo);
-
- dev_dbg(ipu_plane->base.dev->dev,
- "phy = %lu %lu %lu, x = %d, y = %d", eba, ubo, vbo,
- new_state->src.x1 >> 16, new_state->src.y1 >> 16);
- break;
- case DRM_FORMAT_NV12:
- case DRM_FORMAT_NV16:
- ubo = drm_plane_state_to_ubo(new_state);
-
- ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
- fb->pitches[1], ubo, ubo);
-
- dev_dbg(ipu_plane->base.dev->dev,
- "phy = %lu %lu, x = %d, y = %d", eba, ubo,
- new_state->src.x1 >> 16, new_state->src.y1 >> 16);
- break;
- case DRM_FORMAT_RGB565_A8:
- case DRM_FORMAT_BGR565_A8:
- case DRM_FORMAT_RGB888_A8:
- case DRM_FORMAT_BGR888_A8:
- case DRM_FORMAT_RGBX8888_A8:
- case DRM_FORMAT_BGRX8888_A8:
- alpha_eba = drm_plane_state_to_eba(new_state, 1);
- num_bursts = 0;
-
- dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d",
- eba, alpha_eba, new_state->src.x1 >> 16,
- new_state->src.y1 >> 16);
-
- ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
-
- ipu_cpmem_zero(ipu_plane->alpha_ch);
- ipu_cpmem_set_resolution(ipu_plane->alpha_ch, width,
- drm_rect_height(&new_state->src) >> 16);
- ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
- ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
- ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);
- ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]);
- ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16);
- ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba);
- ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba);
- break;
- default:
- dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d",
- eba, new_state->src.x1 >> 16, new_state->src.y1 >> 16);
- break;
- }
- ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
- ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
- ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
- ipu_plane_enable(ipu_plane);
-}
-
-static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
- .atomic_check = ipu_plane_atomic_check,
- .atomic_disable = ipu_plane_atomic_disable,
- .atomic_update = ipu_plane_atomic_update,
-};
-
-bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
-{
- struct ipu_plane *ipu_plane = to_ipu_plane(plane);
- struct drm_plane_state *state = plane->state;
- struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
-
- /* disabled crtcs must not block the update */
- if (!state->crtc)
- return false;
-
- if (ipu_state->use_pre)
- return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
-
- /*
- * Pretend no update is pending in the non-PRE/PRG case. For this to
- * happen, an atomic update would have to be deferred until after the
- * start of the next frame and simultaneously interrupt latency would
- * have to be high enough to let the atomic update finish and issue an
- * event before the previous end of frame interrupt handler can be
- * executed.
- */
- return false;
-}
-int ipu_planes_assign_pre(struct drm_device *dev,
- struct drm_atomic_state *state)
-{
- struct drm_crtc_state *old_crtc_state, *crtc_state;
- struct drm_plane_state *plane_state;
- struct ipu_plane_state *ipu_state;
- struct ipu_plane *ipu_plane;
- struct drm_plane *plane;
- struct drm_crtc *crtc;
- int available_pres = ipu_prg_max_active_channels();
- int ret, i;
-
- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
- ret = drm_atomic_add_affected_planes(state, crtc);
- if (ret)
- return ret;
- }
-
- /*
- * We are going over the planes in 2 passes: first we assign PREs to
- * planes with a tiling modifier, which need the PREs to resolve into
- * linear. Any failure to assign a PRE there is fatal. In the second
- * pass we try to assign PREs to linear FBs, to improve memory access
- * patterns for them. Failure at this point is non-fatal, as we can
- * scan out linear FBs without a PRE.
- */
- for_each_new_plane_in_state(state, plane, plane_state, i) {
- ipu_state = to_ipu_plane_state(plane_state);
- ipu_plane = to_ipu_plane(plane);
-
- if (!plane_state->fb) {
- ipu_state->use_pre = false;
- continue;
- }
-
- if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
- plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
- continue;
-
- if (!ipu_prg_present(ipu_plane->ipu) || !available_pres)
- return -EINVAL;
-
- if (!ipu_prg_format_supported(ipu_plane->ipu,
- plane_state->fb->format->format,
- plane_state->fb->modifier))
- return -EINVAL;
-
- ipu_state->use_pre = true;
- available_pres--;
- }
-
- for_each_new_plane_in_state(state, plane, plane_state, i) {
- ipu_state = to_ipu_plane_state(plane_state);
- ipu_plane = to_ipu_plane(plane);
-
- if (!plane_state->fb) {
- ipu_state->use_pre = false;
- continue;
- }
-
- if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
- plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
- continue;
-
- /* make sure that modifier is initialized */
- plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
-
- if (ipu_prg_present(ipu_plane->ipu) && available_pres &&
- ipu_prg_format_supported(ipu_plane->ipu,
- plane_state->fb->format->format,
- plane_state->fb->modifier)) {
- ipu_state->use_pre = true;
- available_pres--;
- } else {
- ipu_state->use_pre = false;
- }
- }
-
- return 0;
-}
-
-struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
- int dma, int dp, unsigned int possible_crtcs,
- enum drm_plane_type type)
-{
- struct ipu_plane *ipu_plane;
- const uint64_t *modifiers = ipu_format_modifiers;
- unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
- unsigned int format_count;
- const uint32_t *formats;
- int ret;
-
- DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
- dma, dp, possible_crtcs);
-
- if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG) {
- formats = ipu_plane_all_formats;
- format_count = ARRAY_SIZE(ipu_plane_all_formats);
- } else {
- formats = ipu_plane_rgb_formats;
- format_count = ARRAY_SIZE(ipu_plane_rgb_formats);
- }
-
- if (ipu_prg_present(ipu))
- modifiers = pre_format_modifiers;
-
- ipu_plane = drmm_universal_plane_alloc(dev, struct ipu_plane, base,
- possible_crtcs, &ipu_plane_funcs,
- formats, format_count, modifiers,
- type, NULL);
- if (IS_ERR(ipu_plane)) {
- DRM_ERROR("failed to allocate and initialize %s plane\n",
- zpos ? "overlay" : "primary");
- return ipu_plane;
- }
-
- ipu_plane->ipu = ipu;
- ipu_plane->dma = dma;
- ipu_plane->dp_flow = dp;
-
- drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs);
-
- if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG)
- ret = drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0,
- 1);
- else
- ret = drm_plane_create_zpos_immutable_property(&ipu_plane->base,
- 0);
- if (ret)
- return ERR_PTR(ret);
-
- ret = drm_plane_create_color_properties(&ipu_plane->base,
- BIT(DRM_COLOR_YCBCR_BT601) |
- BIT(DRM_COLOR_YCBCR_BT709),
- BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
- DRM_COLOR_YCBCR_BT601,
- DRM_COLOR_YCBCR_LIMITED_RANGE);
- if (ret)
- return ERR_PTR(ret);
-
- ret = ipu_plane_get_resources(dev, ipu_plane);
- if (ret) {
- DRM_ERROR("failed to get %s plane resources: %pe\n",
- zpos ? "overlay" : "primary", &ret);
- return ERR_PTR(ret);
- }
-
- return ipu_plane;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __IPUV3_PLANE_H__
-#define __IPUV3_PLANE_H__
-
-#include <drm/drm_crtc.h> /* drm_plane */
-
-struct drm_plane;
-struct drm_device;
-struct ipu_soc;
-struct drm_crtc;
-struct drm_framebuffer;
-
-struct ipuv3_channel;
-struct dmfc_channel;
-struct ipu_dp;
-
-struct ipu_plane {
- struct drm_plane base;
-
- struct ipu_soc *ipu;
- struct ipuv3_channel *ipu_ch;
- struct ipuv3_channel *alpha_ch;
- struct dmfc_channel *dmfc;
- struct ipu_dp *dp;
-
- int dma;
- int dp_flow;
-
- bool disabling;
-};
-
-struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
- int dma, int dp, unsigned int possible_crtcs,
- enum drm_plane_type type);
-
-/* Init IDMAC, DMFC, DP */
-int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_framebuffer *fb, int crtc_x, int crtc_y,
- unsigned int crtc_w, unsigned int crtc_h,
- uint32_t src_x, uint32_t src_y, uint32_t src_w,
- uint32_t src_h, bool interlaced);
-
-int ipu_plane_irq(struct ipu_plane *plane);
-
-void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel);
-void ipu_plane_disable_deferred(struct drm_plane *plane);
-bool ipu_plane_atomic_update_pending(struct drm_plane *plane);
-
-#endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+config DRM_IMX
+ tristate "DRM Support for Freescale i.MX"
+ select DRM_KMS_HELPER
+ select VIDEOMODE_HELPERS
+ select DRM_GEM_DMA_HELPER
+ depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM || COMPILE_TEST)
+ depends on IMX_IPUV3_CORE
+ help
+ enable i.MX graphics support
+
+config DRM_IMX_PARALLEL_DISPLAY
+ tristate "Support for parallel displays"
+ select DRM_PANEL
+ depends on DRM_IMX
+ select VIDEOMODE_HELPERS
+
+config DRM_IMX_TVE
+ tristate "Support for TV and VGA displays"
+ depends on DRM_IMX
+ depends on COMMON_CLK
+ select REGMAP_MMIO
+ help
+ Choose this to enable the internal Television Encoder (TVe)
+ found on i.MX53 processors.
+
+config DRM_IMX_LDB
+ tristate "Support for LVDS displays"
+ depends on DRM_IMX && MFD_SYSCON
+ depends on COMMON_CLK
+ select DRM_PANEL
+ help
+ Choose this to enable the internal LVDS Display Bridge (LDB)
+ found on i.MX53 and i.MX6 processors.
+
+config DRM_IMX_HDMI
+ tristate "Freescale i.MX DRM HDMI"
+ select DRM_DW_HDMI
+ depends on DRM_IMX && OF
+ help
+ Choose this if you want to use HDMI on i.MX6.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+imxdrm-objs := imx-drm-core.o ipuv3-crtc.o ipuv3-plane.o
+
+obj-$(CONFIG_DRM_IMX) += imxdrm.o
+
+obj-$(CONFIG_DRM_IMX_PARALLEL_DISPLAY) += parallel-display.o
+obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
+obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
+
+obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
+ */
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <video/imx-ipu-v3.h>
+
+#include <drm/bridge/dw_hdmi.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_of.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include "imx-drm.h"
+
+struct imx_hdmi;
+
+struct imx_hdmi_encoder {
+ struct drm_encoder encoder;
+ struct imx_hdmi *hdmi;
+};
+
+struct imx_hdmi {
+ struct device *dev;
+ struct drm_bridge *bridge;
+ struct dw_hdmi *hdmi;
+ struct regmap *regmap;
+};
+
+static inline struct imx_hdmi *enc_to_imx_hdmi(struct drm_encoder *e)
+{
+ return container_of(e, struct imx_hdmi_encoder, encoder)->hdmi;
+}
+
+static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
+ {
+ 45250000, {
+ { 0x01e0, 0x0000 },
+ { 0x21e1, 0x0000 },
+ { 0x41e2, 0x0000 }
+ },
+ }, {
+ 92500000, {
+ { 0x0140, 0x0005 },
+ { 0x2141, 0x0005 },
+ { 0x4142, 0x0005 },
+ },
+ }, {
+ 148500000, {
+ { 0x00a0, 0x000a },
+ { 0x20a1, 0x000a },
+ { 0x40a2, 0x000a },
+ },
+ }, {
+ 216000000, {
+ { 0x00a0, 0x000a },
+ { 0x2001, 0x000f },
+ { 0x4002, 0x000f },
+ },
+ }, {
+ ~0UL, {
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ },
+ }
+};
+
+static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
+ /* pixelclk bpp8 bpp10 bpp12 */
+ {
+ 54000000, { 0x091c, 0x091c, 0x06dc },
+ }, {
+ 58400000, { 0x091c, 0x06dc, 0x06dc },
+ }, {
+ 72000000, { 0x06dc, 0x06dc, 0x091c },
+ }, {
+ 74250000, { 0x06dc, 0x0b5c, 0x091c },
+ }, {
+ 118800000, { 0x091c, 0x091c, 0x06dc },
+ }, {
+ 216000000, { 0x06dc, 0x0b5c, 0x091c },
+ }, {
+ ~0UL, { 0x0000, 0x0000, 0x0000 },
+ },
+};
+
+/*
+ * Resistance term 133Ohm Cfg
+ * PREEMP config 0.00
+ * TX/CK level 10
+ */
+static const struct dw_hdmi_phy_config imx_phy_config[] = {
+ /*pixelclk symbol term vlev */
+ { 216000000, 0x800d, 0x0005, 0x01ad},
+ { ~0UL, 0x0000, 0x0000, 0x0000}
+};
+
+static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
+{
+ struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
+ int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
+
+ regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
+ IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
+ mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
+}
+
+static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
+
+ imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ imx_crtc_state->di_hsync_pin = 2;
+ imx_crtc_state->di_vsync_pin = 3;
+
+ return 0;
+}
+
+static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
+ .enable = dw_hdmi_imx_encoder_enable,
+ .atomic_check = dw_hdmi_imx_atomic_check,
+};
+
+static enum drm_mode_status
+imx6q_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock < 13500)
+ return MODE_CLOCK_LOW;
+ /* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
+ if (mode->clock > 216000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static enum drm_mode_status
+imx6dl_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock < 13500)
+ return MODE_CLOCK_LOW;
+ /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
+ if (mode->clock > 216000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
+ .mpll_cfg = imx_mpll_cfg,
+ .cur_ctr = imx_cur_ctr,
+ .phy_config = imx_phy_config,
+ .mode_valid = imx6q_hdmi_mode_valid,
+};
+
+static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
+ .mpll_cfg = imx_mpll_cfg,
+ .cur_ctr = imx_cur_ctr,
+ .phy_config = imx_phy_config,
+ .mode_valid = imx6dl_hdmi_mode_valid,
+};
+
+static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
+ { .compatible = "fsl,imx6q-hdmi",
+ .data = &imx6q_hdmi_drv_data
+ }, {
+ .compatible = "fsl,imx6dl-hdmi",
+ .data = &imx6dl_hdmi_drv_data
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
+
+static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct drm_device *drm = data;
+ struct imx_hdmi_encoder *hdmi_encoder;
+ struct drm_encoder *encoder;
+ int ret;
+
+ hdmi_encoder = drmm_simple_encoder_alloc(drm, struct imx_hdmi_encoder,
+ encoder, DRM_MODE_ENCODER_TMDS);
+ if (IS_ERR(hdmi_encoder))
+ return PTR_ERR(hdmi_encoder);
+
+ hdmi_encoder->hdmi = dev_get_drvdata(dev);
+ encoder = &hdmi_encoder->encoder;
+
+ ret = imx_drm_encoder_parse_of(drm, encoder, dev->of_node);
+ if (ret)
+ return ret;
+
+ drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
+
+ return drm_bridge_attach(encoder, hdmi_encoder->hdmi->bridge, NULL, 0);
+}
+
+static const struct component_ops dw_hdmi_imx_ops = {
+ .bind = dw_hdmi_imx_bind,
+};
+
+static int dw_hdmi_imx_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match = of_match_node(dw_hdmi_imx_dt_ids, np);
+ struct imx_hdmi *hdmi;
+ int ret;
+
+ hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
+ if (!hdmi)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, hdmi);
+ hdmi->dev = &pdev->dev;
+
+ hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
+ if (IS_ERR(hdmi->regmap)) {
+ dev_err(hdmi->dev, "Unable to get gpr\n");
+ return PTR_ERR(hdmi->regmap);
+ }
+
+ hdmi->hdmi = dw_hdmi_probe(pdev, match->data);
+ if (IS_ERR(hdmi->hdmi))
+ return PTR_ERR(hdmi->hdmi);
+
+ hdmi->bridge = of_drm_find_bridge(np);
+ if (!hdmi->bridge) {
+ dev_err(hdmi->dev, "Unable to find bridge\n");
+ dw_hdmi_remove(hdmi->hdmi);
+ return -ENODEV;
+ }
+
+ ret = component_add(&pdev->dev, &dw_hdmi_imx_ops);
+ if (ret)
+ dw_hdmi_remove(hdmi->hdmi);
+
+ return ret;
+}
+
+static int dw_hdmi_imx_remove(struct platform_device *pdev)
+{
+ struct imx_hdmi *hdmi = platform_get_drvdata(pdev);
+
+ component_del(&pdev->dev, &dw_hdmi_imx_ops);
+ dw_hdmi_remove(hdmi->hdmi);
+
+ return 0;
+}
+
+static struct platform_driver dw_hdmi_imx_platform_driver = {
+ .probe = dw_hdmi_imx_probe,
+ .remove = dw_hdmi_imx_remove,
+ .driver = {
+ .name = "dwhdmi-imx",
+ .of_match_table = dw_hdmi_imx_dt_ids,
+ },
+};
+
+module_platform_driver(dw_hdmi_imx_platform_driver);
+
+MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dwhdmi-imx");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale i.MX drm driver
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix
+ */
+
+#include <linux/component.h>
+#include <linux/device.h>
+#include <linux/dma-buf.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <video/imx-ipu-v3.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fbdev_generic.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "imx-drm.h"
+#include "ipuv3-plane.h"
+
+#define MAX_CRTC 4
+
+static int legacyfb_depth = 16;
+module_param(legacyfb_depth, int, 0444);
+
+DEFINE_DRM_GEM_DMA_FOPS(imx_drm_driver_fops);
+
+void imx_drm_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_unregister(connector);
+ drm_connector_cleanup(connector);
+}
+EXPORT_SYMBOL_GPL(imx_drm_connector_destroy);
+
+static int imx_drm_atomic_check(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ int ret;
+
+ ret = drm_atomic_helper_check(dev, state);
+ if (ret)
+ return ret;
+
+ /*
+ * Check modeset again in case crtc_state->mode_changed is
+ * updated in plane's ->atomic_check callback.
+ */
+ ret = drm_atomic_helper_check_modeset(dev, state);
+ if (ret)
+ return ret;
+
+ /* Assign PRG/PRE channels and check if all constrains are satisfied. */
+ ret = ipu_planes_assign_pre(dev, state);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
+static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
+ .fb_create = drm_gem_fb_create,
+ .atomic_check = imx_drm_atomic_check,
+ .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
+{
+ struct drm_device *dev = state->dev;
+ struct drm_plane *plane;
+ struct drm_plane_state *old_plane_state, *new_plane_state;
+ bool plane_disabling = false;
+ int i;
+
+ drm_atomic_helper_commit_modeset_disables(dev, state);
+
+ drm_atomic_helper_commit_planes(dev, state,
+ DRM_PLANE_COMMIT_ACTIVE_ONLY |
+ DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET);
+
+ drm_atomic_helper_commit_modeset_enables(dev, state);
+
+ for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
+ if (drm_atomic_plane_disabling(old_plane_state, new_plane_state))
+ plane_disabling = true;
+ }
+
+ /*
+ * The flip done wait is only strictly required by imx-drm if a deferred
+ * plane disable is in-flight. As the core requires blocking commits
+ * to wait for the flip it is done here unconditionally. This keeps the
+ * workitem around a bit longer than required for the majority of
+ * non-blocking commits, but we accept that for the sake of simplicity.
+ */
+ drm_atomic_helper_wait_for_flip_done(dev, state);
+
+ if (plane_disabling) {
+ for_each_old_plane_in_state(state, plane, old_plane_state, i)
+ ipu_plane_disable_deferred(plane);
+
+ }
+
+ drm_atomic_helper_commit_hw_done(state);
+}
+
+static const struct drm_mode_config_helper_funcs imx_drm_mode_config_helpers = {
+ .atomic_commit_tail = imx_drm_atomic_commit_tail,
+};
+
+
+int imx_drm_encoder_parse_of(struct drm_device *drm,
+ struct drm_encoder *encoder, struct device_node *np)
+{
+ uint32_t crtc_mask = drm_of_find_possible_crtcs(drm, np);
+
+ /*
+ * If we failed to find the CRTC(s) which this encoder is
+ * supposed to be connected to, it's because the CRTC has
+ * not been registered yet. Defer probing, and hope that
+ * the required CRTC is added later.
+ */
+ if (crtc_mask == 0)
+ return -EPROBE_DEFER;
+
+ encoder->possible_crtcs = crtc_mask;
+
+ /* FIXME: cloning support not clear, disable it all for now */
+ encoder->possible_clones = 0;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of);
+
+static const struct drm_ioctl_desc imx_drm_ioctls[] = {
+ /* none so far */
+};
+
+static int imx_drm_dumb_create(struct drm_file *file_priv,
+ struct drm_device *drm,
+ struct drm_mode_create_dumb *args)
+{
+ u32 width = args->width;
+ int ret;
+
+ args->width = ALIGN(width, 8);
+
+ ret = drm_gem_dma_dumb_create(file_priv, drm, args);
+ if (ret)
+ return ret;
+
+ args->width = width;
+ return ret;
+}
+
+static const struct drm_driver imx_drm_driver = {
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
+ DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(imx_drm_dumb_create),
+ .ioctls = imx_drm_ioctls,
+ .num_ioctls = ARRAY_SIZE(imx_drm_ioctls),
+ .fops = &imx_drm_driver_fops,
+ .name = "imx-drm",
+ .desc = "i.MX DRM graphics",
+ .date = "20120507",
+ .major = 1,
+ .minor = 0,
+ .patchlevel = 0,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+ struct device_node *np = data;
+
+ /* Special case for DI, dev->of_node may not be set yet */
+ if (strcmp(dev->driver->name, "imx-ipuv3-crtc") == 0) {
+ struct ipu_client_platformdata *pdata = dev->platform_data;
+
+ return pdata->of_node == np;
+ }
+
+ /* Special case for LDB, one device for two channels */
+ if (of_node_name_eq(np, "lvds-channel")) {
+ np = of_get_parent(np);
+ of_node_put(np);
+ }
+
+ return dev->of_node == np;
+}
+
+static int imx_drm_bind(struct device *dev)
+{
+ struct drm_device *drm;
+ int ret;
+
+ drm = drm_dev_alloc(&imx_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+
+ /*
+ * set max width and height as default value(4096x4096).
+ * this value would be used to check framebuffer size limitation
+ * at drm_mode_addfb().
+ */
+ drm->mode_config.min_width = 1;
+ drm->mode_config.min_height = 1;
+ drm->mode_config.max_width = 4096;
+ drm->mode_config.max_height = 4096;
+ drm->mode_config.funcs = &imx_drm_mode_config_funcs;
+ drm->mode_config.helper_private = &imx_drm_mode_config_helpers;
+ drm->mode_config.normalize_zpos = true;
+
+ ret = drmm_mode_config_init(drm);
+ if (ret)
+ goto err_kms;
+
+ ret = drm_vblank_init(drm, MAX_CRTC);
+ if (ret)
+ goto err_kms;
+
+ dev_set_drvdata(dev, drm);
+
+ /* Now try and bind all our sub-components */
+ ret = component_bind_all(dev, drm);
+ if (ret)
+ goto err_kms;
+
+ drm_mode_config_reset(drm);
+
+ /*
+ * All components are now initialised, so setup the fb helper.
+ * The fb helper takes copies of key hardware information, so the
+ * crtcs/connectors/encoders must not change after this point.
+ */
+ if (legacyfb_depth != 16 && legacyfb_depth != 32) {
+ dev_warn(dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n");
+ legacyfb_depth = 16;
+ }
+
+ drm_kms_helper_poll_init(drm);
+
+ ret = drm_dev_register(drm, 0);
+ if (ret)
+ goto err_poll_fini;
+
+ drm_fbdev_generic_setup(drm, legacyfb_depth);
+
+ return 0;
+
+err_poll_fini:
+ drm_kms_helper_poll_fini(drm);
+ component_unbind_all(drm->dev, drm);
+err_kms:
+ drm_dev_put(drm);
+
+ return ret;
+}
+
+static void imx_drm_unbind(struct device *dev)
+{
+ struct drm_device *drm = dev_get_drvdata(dev);
+
+ drm_dev_unregister(drm);
+
+ drm_kms_helper_poll_fini(drm);
+
+ component_unbind_all(drm->dev, drm);
+
+ drm_dev_put(drm);
+
+ dev_set_drvdata(dev, NULL);
+}
+
+static const struct component_master_ops imx_drm_ops = {
+ .bind = imx_drm_bind,
+ .unbind = imx_drm_unbind,
+};
+
+static int imx_drm_platform_probe(struct platform_device *pdev)
+{
+ int ret = drm_of_component_probe(&pdev->dev, compare_of, &imx_drm_ops);
+
+ if (!ret)
+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+
+ return ret;
+}
+
+static int imx_drm_platform_remove(struct platform_device *pdev)
+{
+ component_master_del(&pdev->dev, &imx_drm_ops);
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int imx_drm_suspend(struct device *dev)
+{
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+ return drm_mode_config_helper_suspend(drm_dev);
+}
+
+static int imx_drm_resume(struct device *dev)
+{
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+ return drm_mode_config_helper_resume(drm_dev);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(imx_drm_pm_ops, imx_drm_suspend, imx_drm_resume);
+
+static const struct of_device_id imx_drm_dt_ids[] = {
+ { .compatible = "fsl,imx-display-subsystem", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx_drm_dt_ids);
+
+static struct platform_driver imx_drm_pdrv = {
+ .probe = imx_drm_platform_probe,
+ .remove = imx_drm_platform_remove,
+ .driver = {
+ .name = "imx-drm",
+ .pm = &imx_drm_pm_ops,
+ .of_match_table = imx_drm_dt_ids,
+ },
+};
+
+static struct platform_driver * const drivers[] = {
+ &imx_drm_pdrv,
+ &ipu_drm_driver,
+};
+
+static int __init imx_drm_init(void)
+{
+ if (drm_firmware_drivers_only())
+ return -ENODEV;
+
+ return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
+}
+module_init(imx_drm_init);
+
+static void __exit imx_drm_exit(void)
+{
+ platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
+}
+module_exit(imx_drm_exit);
+
+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+MODULE_DESCRIPTION("i.MX drm driver core");
+MODULE_LICENSE("GPL");
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _IMX_DRM_H_
+#define _IMX_DRM_H_
+
+struct device_node;
+struct drm_crtc;
+struct drm_connector;
+struct drm_device;
+struct drm_display_mode;
+struct drm_encoder;
+struct drm_framebuffer;
+struct drm_plane;
+struct platform_device;
+
+struct imx_crtc_state {
+ struct drm_crtc_state base;
+ u32 bus_format;
+ u32 bus_flags;
+ int di_hsync_pin;
+ int di_vsync_pin;
+};
+
+static inline struct imx_crtc_state *to_imx_crtc_state(struct drm_crtc_state *s)
+{
+ return container_of(s, struct imx_crtc_state, base);
+}
+int imx_drm_init_drm(struct platform_device *pdev,
+ int preferred_bpp);
+int imx_drm_exit_drm(void);
+
+extern struct platform_driver ipu_drm_driver;
+
+void imx_drm_mode_config_init(struct drm_device *drm);
+
+struct drm_gem_dma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
+
+int imx_drm_encoder_parse_of(struct drm_device *drm,
+ struct drm_encoder *encoder, struct device_node *np);
+
+void imx_drm_connector_destroy(struct drm_connector *connector);
+
+int ipu_planes_assign_pre(struct drm_device *dev,
+ struct drm_atomic_state *state);
+
+#endif /* _IMX_DRM_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX drm driver - LVDS display bridge
+ *
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/i2c.h>
+#include <linux/media-bus-format.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/videodev2.h>
+
+#include <video/of_display_timing.h>
+#include <video/of_videomode.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include "imx-drm.h"
+
+#define DRIVER_NAME "imx-ldb"
+
+#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
+#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
+#define LDB_CH0_MODE_EN_MASK (3 << 0)
+#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
+#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
+#define LDB_CH1_MODE_EN_MASK (3 << 2)
+#define LDB_SPLIT_MODE_EN (1 << 4)
+#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
+#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
+#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
+#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
+#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
+#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
+#define LDB_BGREF_RMODE_INT (1 << 15)
+
+struct imx_ldb_channel;
+
+struct imx_ldb_encoder {
+ struct drm_connector connector;
+ struct drm_encoder encoder;
+ struct imx_ldb_channel *channel;
+};
+
+struct imx_ldb;
+
+struct imx_ldb_channel {
+ struct imx_ldb *ldb;
+
+ /* Defines what is connected to the ldb, only one at a time */
+ struct drm_panel *panel;
+ struct drm_bridge *bridge;
+
+ struct device_node *child;
+ struct i2c_adapter *ddc;
+ int chno;
+ void *edid;
+ struct drm_display_mode mode;
+ int mode_valid;
+ u32 bus_format;
+ u32 bus_flags;
+};
+
+static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
+{
+ return container_of(c, struct imx_ldb_encoder, connector)->channel;
+}
+
+static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
+{
+ return container_of(e, struct imx_ldb_encoder, encoder)->channel;
+}
+
+struct bus_mux {
+ int reg;
+ int shift;
+ int mask;
+};
+
+struct imx_ldb {
+ struct regmap *regmap;
+ struct device *dev;
+ struct imx_ldb_channel channel[2];
+ struct clk *clk[2]; /* our own clock */
+ struct clk *clk_sel[4]; /* parent of display clock */
+ struct clk *clk_parent[4]; /* original parent of clk_sel */
+ struct clk *clk_pll[2]; /* upstream clock we can adjust */
+ u32 ldb_ctrl;
+ const struct bus_mux *lvds_mux;
+};
+
+static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
+ u32 bus_format)
+{
+ struct imx_ldb *ldb = imx_ldb_ch->ldb;
+ int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
+
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ if (imx_ldb_ch->chno == 0 || dual)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
+ if (imx_ldb_ch->chno == 1 || dual)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ if (imx_ldb_ch->chno == 0 || dual)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
+ LDB_BIT_MAP_CH0_JEIDA;
+ if (imx_ldb_ch->chno == 1 || dual)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
+ LDB_BIT_MAP_CH1_JEIDA;
+ break;
+ }
+}
+
+static int imx_ldb_connector_get_modes(struct drm_connector *connector)
+{
+ struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
+ int num_modes;
+
+ num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);
+ if (num_modes > 0)
+ return num_modes;
+
+ if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
+ imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
+
+ if (imx_ldb_ch->edid) {
+ drm_connector_update_edid_property(connector,
+ imx_ldb_ch->edid);
+ num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
+ }
+
+ if (imx_ldb_ch->mode_valid) {
+ struct drm_display_mode *mode;
+
+ mode = drm_mode_duplicate(connector->dev, &imx_ldb_ch->mode);
+ if (!mode)
+ return -EINVAL;
+ mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+ drm_mode_probed_add(connector, mode);
+ num_modes++;
+ }
+
+ return num_modes;
+}
+
+static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
+ unsigned long serial_clk, unsigned long di_clk)
+{
+ int ret;
+
+ dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
+ clk_get_rate(ldb->clk_pll[chno]), serial_clk);
+ clk_set_rate(ldb->clk_pll[chno], serial_clk);
+
+ dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
+ clk_get_rate(ldb->clk_pll[chno]));
+
+ dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
+ clk_get_rate(ldb->clk[chno]),
+ (long int)di_clk);
+ clk_set_rate(ldb->clk[chno], di_clk);
+
+ dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
+ clk_get_rate(ldb->clk[chno]));
+
+ /* set display clock mux to LDB input clock */
+ ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
+ if (ret)
+ dev_err(ldb->dev,
+ "unable to set di%d parent clock to ldb_di%d\n", mux,
+ chno);
+}
+
+static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
+{
+ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+ struct imx_ldb *ldb = imx_ldb_ch->ldb;
+ int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
+ int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
+
+ if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
+ dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
+ return;
+ }
+
+ drm_panel_prepare(imx_ldb_ch->panel);
+
+ if (dual) {
+ clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
+ clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
+
+ clk_prepare_enable(ldb->clk[0]);
+ clk_prepare_enable(ldb->clk[1]);
+ } else {
+ clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
+ }
+
+ if (imx_ldb_ch == &ldb->channel[0] || dual) {
+ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+ if (mux == 0 || ldb->lvds_mux)
+ ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
+ else if (mux == 1)
+ ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
+ }
+ if (imx_ldb_ch == &ldb->channel[1] || dual) {
+ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+ if (mux == 1 || ldb->lvds_mux)
+ ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
+ else if (mux == 0)
+ ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
+ }
+
+ if (ldb->lvds_mux) {
+ const struct bus_mux *lvds_mux = NULL;
+
+ if (imx_ldb_ch == &ldb->channel[0])
+ lvds_mux = &ldb->lvds_mux[0];
+ else if (imx_ldb_ch == &ldb->channel[1])
+ lvds_mux = &ldb->lvds_mux[1];
+
+ regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
+ mux << lvds_mux->shift);
+ }
+
+ regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
+
+ drm_panel_enable(imx_ldb_ch->panel);
+}
+
+static void
+imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *connector_state)
+{
+ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+ struct drm_display_mode *mode = &crtc_state->adjusted_mode;
+ struct imx_ldb *ldb = imx_ldb_ch->ldb;
+ int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
+ unsigned long serial_clk;
+ unsigned long di_clk = mode->clock * 1000;
+ int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
+ u32 bus_format = imx_ldb_ch->bus_format;
+
+ if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
+ dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
+ return;
+ }
+
+ if (mode->clock > 170000) {
+ dev_warn(ldb->dev,
+ "%s: mode exceeds 170 MHz pixel clock\n", __func__);
+ }
+ if (mode->clock > 85000 && !dual) {
+ dev_warn(ldb->dev,
+ "%s: mode exceeds 85 MHz pixel clock\n", __func__);
+ }
+
+ if (!IS_ALIGNED(mode->hdisplay, 8)) {
+ dev_warn(ldb->dev,
+ "%s: hdisplay does not align to 8 byte\n", __func__);
+ }
+
+ if (dual) {
+ serial_clk = 3500UL * mode->clock;
+ imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
+ imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
+ } else {
+ serial_clk = 7000UL * mode->clock;
+ imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
+ di_clk);
+ }
+
+ /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
+ if (imx_ldb_ch == &ldb->channel[0] || dual) {
+ if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+ ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
+ else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+ ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
+ }
+ if (imx_ldb_ch == &ldb->channel[1] || dual) {
+ if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+ ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
+ else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+ ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
+ }
+
+ if (!bus_format) {
+ struct drm_connector *connector = connector_state->connector;
+ struct drm_display_info *di = &connector->display_info;
+
+ if (di->num_bus_formats)
+ bus_format = di->bus_formats[0];
+ }
+ imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
+}
+
+static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
+{
+ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+ struct imx_ldb *ldb = imx_ldb_ch->ldb;
+ int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
+ int mux, ret;
+
+ drm_panel_disable(imx_ldb_ch->panel);
+
+ if (imx_ldb_ch == &ldb->channel[0] || dual)
+ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+ if (imx_ldb_ch == &ldb->channel[1] || dual)
+ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+
+ regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
+
+ if (dual) {
+ clk_disable_unprepare(ldb->clk[0]);
+ clk_disable_unprepare(ldb->clk[1]);
+ }
+
+ if (ldb->lvds_mux) {
+ const struct bus_mux *lvds_mux = NULL;
+
+ if (imx_ldb_ch == &ldb->channel[0])
+ lvds_mux = &ldb->lvds_mux[0];
+ else if (imx_ldb_ch == &ldb->channel[1])
+ lvds_mux = &ldb->lvds_mux[1];
+
+ regmap_read(ldb->regmap, lvds_mux->reg, &mux);
+ mux &= lvds_mux->mask;
+ mux >>= lvds_mux->shift;
+ } else {
+ mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
+ }
+
+ /* set display clock mux back to original input clock */
+ ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
+ if (ret)
+ dev_err(ldb->dev,
+ "unable to set di%d parent clock to original parent\n",
+ mux);
+
+ drm_panel_unprepare(imx_ldb_ch->panel);
+}
+
+static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
+ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+ struct drm_display_info *di = &conn_state->connector->display_info;
+ u32 bus_format = imx_ldb_ch->bus_format;
+
+ /* Bus format description in DT overrides connector display info. */
+ if (!bus_format && di->num_bus_formats) {
+ bus_format = di->bus_formats[0];
+ imx_crtc_state->bus_flags = di->bus_flags;
+ } else {
+ bus_format = imx_ldb_ch->bus_format;
+ imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
+ }
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ imx_crtc_state->di_hsync_pin = 2;
+ imx_crtc_state->di_vsync_pin = 3;
+
+ return 0;
+}
+
+
+static const struct drm_connector_funcs imx_ldb_connector_funcs = {
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = imx_drm_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
+ .get_modes = imx_ldb_connector_get_modes,
+};
+
+static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
+ .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
+ .enable = imx_ldb_encoder_enable,
+ .disable = imx_ldb_encoder_disable,
+ .atomic_check = imx_ldb_encoder_atomic_check,
+};
+
+static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
+{
+ char clkname[16];
+
+ snprintf(clkname, sizeof(clkname), "di%d", chno);
+ ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
+ if (IS_ERR(ldb->clk[chno]))
+ return PTR_ERR(ldb->clk[chno]);
+
+ snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
+ ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
+
+ return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
+}
+
+static int imx_ldb_register(struct drm_device *drm,
+ struct imx_ldb_channel *imx_ldb_ch)
+{
+ struct imx_ldb *ldb = imx_ldb_ch->ldb;
+ struct imx_ldb_encoder *ldb_encoder;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+ int ret;
+
+ ldb_encoder = drmm_simple_encoder_alloc(drm, struct imx_ldb_encoder,
+ encoder, DRM_MODE_ENCODER_LVDS);
+ if (IS_ERR(ldb_encoder))
+ return PTR_ERR(ldb_encoder);
+
+ ldb_encoder->channel = imx_ldb_ch;
+ connector = &ldb_encoder->connector;
+ encoder = &ldb_encoder->encoder;
+
+ ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
+ if (ret)
+ return ret;
+
+ ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
+ if (ret)
+ return ret;
+
+ if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
+ ret = imx_ldb_get_clk(ldb, 1);
+ if (ret)
+ return ret;
+ }
+
+ drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
+
+ if (imx_ldb_ch->bridge) {
+ ret = drm_bridge_attach(encoder, imx_ldb_ch->bridge, NULL, 0);
+ if (ret)
+ return ret;
+ } else {
+ /*
+ * We want to add the connector whenever there is no bridge
+ * that brings its own, not only when there is a panel. For
+ * historical reasons, the ldb driver can also work without
+ * a panel.
+ */
+ drm_connector_helper_add(connector,
+ &imx_ldb_connector_helper_funcs);
+ drm_connector_init_with_ddc(drm, connector,
+ &imx_ldb_connector_funcs,
+ DRM_MODE_CONNECTOR_LVDS,
+ imx_ldb_ch->ddc);
+ drm_connector_attach_encoder(connector, encoder);
+ }
+
+ return 0;
+}
+
+struct imx_ldb_bit_mapping {
+ u32 bus_format;
+ u32 datawidth;
+ const char * const mapping;
+};
+
+static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
+ { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
+ { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
+ { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
+};
+
+static u32 of_get_bus_format(struct device *dev, struct device_node *np)
+{
+ const char *bm;
+ u32 datawidth = 0;
+ int ret, i;
+
+ ret = of_property_read_string(np, "fsl,data-mapping", &bm);
+ if (ret < 0)
+ return ret;
+
+ of_property_read_u32(np, "fsl,data-width", &datawidth);
+
+ for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
+ if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
+ datawidth == imx_ldb_bit_mappings[i].datawidth)
+ return imx_ldb_bit_mappings[i].bus_format;
+ }
+
+ dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
+
+ return -ENOENT;
+}
+
+static struct bus_mux imx6q_lvds_mux[2] = {
+ {
+ .reg = IOMUXC_GPR3,
+ .shift = 6,
+ .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
+ }, {
+ .reg = IOMUXC_GPR3,
+ .shift = 8,
+ .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
+ }
+};
+
+/*
+ * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
+ * of_match_device will walk through this list and take the first entry
+ * matching any of its compatible values. Therefore, the more generic
+ * entries (in this case fsl,imx53-ldb) need to be ordered last.
+ */
+static const struct of_device_id imx_ldb_dt_ids[] = {
+ { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
+ { .compatible = "fsl,imx53-ldb", .data = NULL, },
+ { }
+};
+MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
+
+static int imx_ldb_panel_ddc(struct device *dev,
+ struct imx_ldb_channel *channel, struct device_node *child)
+{
+ struct device_node *ddc_node;
+ const u8 *edidp;
+ int ret;
+
+ ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
+ if (ddc_node) {
+ channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
+ of_node_put(ddc_node);
+ if (!channel->ddc) {
+ dev_warn(dev, "failed to get ddc i2c adapter\n");
+ return -EPROBE_DEFER;
+ }
+ }
+
+ if (!channel->ddc) {
+ int edid_len;
+
+ /* if no DDC available, fallback to hardcoded EDID */
+ dev_dbg(dev, "no ddc available\n");
+
+ edidp = of_get_property(child, "edid", &edid_len);
+ if (edidp) {
+ channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
+ if (!channel->edid)
+ return -ENOMEM;
+ } else if (!channel->panel) {
+ /* fallback to display-timings node */
+ ret = of_get_drm_display_mode(child,
+ &channel->mode,
+ &channel->bus_flags,
+ OF_USE_NATIVE_MODE);
+ if (!ret)
+ channel->mode_valid = 1;
+ }
+ }
+ return 0;
+}
+
+static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
+{
+ struct drm_device *drm = data;
+ struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
+ int ret;
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ struct imx_ldb_channel *channel = &imx_ldb->channel[i];
+
+ if (!channel->ldb)
+ continue;
+
+ ret = imx_ldb_register(drm, channel);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct component_ops imx_ldb_ops = {
+ .bind = imx_ldb_bind,
+};
+
+static int imx_ldb_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const struct of_device_id *of_id = of_match_device(imx_ldb_dt_ids, dev);
+ struct device_node *child;
+ struct imx_ldb *imx_ldb;
+ int dual;
+ int ret;
+ int i;
+
+ imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
+ if (!imx_ldb)
+ return -ENOMEM;
+
+ imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
+ if (IS_ERR(imx_ldb->regmap)) {
+ dev_err(dev, "failed to get parent regmap\n");
+ return PTR_ERR(imx_ldb->regmap);
+ }
+
+ /* disable LDB by resetting the control register to POR default */
+ regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
+
+ imx_ldb->dev = dev;
+
+ if (of_id)
+ imx_ldb->lvds_mux = of_id->data;
+
+ dual = of_property_read_bool(np, "fsl,dual-channel");
+ if (dual)
+ imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
+
+ /*
+ * There are three different possible clock mux configurations:
+ * i.MX53: ipu1_di0_sel, ipu1_di1_sel
+ * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
+ * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
+ * Map them all to di0_sel...di3_sel.
+ */
+ for (i = 0; i < 4; i++) {
+ char clkname[16];
+
+ sprintf(clkname, "di%d_sel", i);
+ imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
+ if (IS_ERR(imx_ldb->clk_sel[i])) {
+ ret = PTR_ERR(imx_ldb->clk_sel[i]);
+ imx_ldb->clk_sel[i] = NULL;
+ break;
+ }
+
+ imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
+ }
+ if (i == 0)
+ return ret;
+
+ for_each_child_of_node(np, child) {
+ struct imx_ldb_channel *channel;
+ int bus_format;
+
+ ret = of_property_read_u32(child, "reg", &i);
+ if (ret || i < 0 || i > 1) {
+ ret = -EINVAL;
+ goto free_child;
+ }
+
+ if (!of_device_is_available(child))
+ continue;
+
+ if (dual && i > 0) {
+ dev_warn(dev, "dual-channel mode, ignoring second output\n");
+ continue;
+ }
+
+ channel = &imx_ldb->channel[i];
+ channel->ldb = imx_ldb;
+ channel->chno = i;
+
+ /*
+ * The output port is port@4 with an external 4-port mux or
+ * port@2 with the internal 2-port mux.
+ */
+ ret = drm_of_find_panel_or_bridge(child,
+ imx_ldb->lvds_mux ? 4 : 2, 0,
+ &channel->panel, &channel->bridge);
+ if (ret && ret != -ENODEV)
+ goto free_child;
+
+ /* panel ddc only if there is no bridge */
+ if (!channel->bridge) {
+ ret = imx_ldb_panel_ddc(dev, channel, child);
+ if (ret)
+ goto free_child;
+ }
+
+ bus_format = of_get_bus_format(dev, child);
+ if (bus_format == -EINVAL) {
+ /*
+ * If no bus format was specified in the device tree,
+ * we can still get it from the connected panel later.
+ */
+ if (channel->panel && channel->panel->funcs &&
+ channel->panel->funcs->get_modes)
+ bus_format = 0;
+ }
+ if (bus_format < 0) {
+ dev_err(dev, "could not determine data mapping: %d\n",
+ bus_format);
+ ret = bus_format;
+ goto free_child;
+ }
+ channel->bus_format = bus_format;
+ channel->child = child;
+ }
+
+ platform_set_drvdata(pdev, imx_ldb);
+
+ return component_add(&pdev->dev, &imx_ldb_ops);
+
+free_child:
+ of_node_put(child);
+ return ret;
+}
+
+static int imx_ldb_remove(struct platform_device *pdev)
+{
+ struct imx_ldb *imx_ldb = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ struct imx_ldb_channel *channel = &imx_ldb->channel[i];
+
+ kfree(channel->edid);
+ i2c_put_adapter(channel->ddc);
+ }
+
+ component_del(&pdev->dev, &imx_ldb_ops);
+ return 0;
+}
+
+static struct platform_driver imx_ldb_driver = {
+ .probe = imx_ldb_probe,
+ .remove = imx_ldb_remove,
+ .driver = {
+ .of_match_table = imx_ldb_dt_ids,
+ .name = DRIVER_NAME,
+ },
+};
+
+module_platform_driver(imx_ldb_driver);
+
+MODULE_DESCRIPTION("i.MX LVDS driver");
+MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX drm driver - Television Encoder (TVEv2)
+ *
+ * Copyright (C) 2013 Philipp Zabel, Pengutronix
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/videodev2.h>
+
+#include <video/imx-ipu-v3.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include "imx-drm.h"
+
+#define TVE_COM_CONF_REG 0x00
+#define TVE_TVDAC0_CONT_REG 0x28
+#define TVE_TVDAC1_CONT_REG 0x2c
+#define TVE_TVDAC2_CONT_REG 0x30
+#define TVE_CD_CONT_REG 0x34
+#define TVE_INT_CONT_REG 0x64
+#define TVE_STAT_REG 0x68
+#define TVE_TST_MODE_REG 0x6c
+#define TVE_MV_CONT_REG 0xdc
+
+/* TVE_COM_CONF_REG */
+#define TVE_SYNC_CH_2_EN BIT(22)
+#define TVE_SYNC_CH_1_EN BIT(21)
+#define TVE_SYNC_CH_0_EN BIT(20)
+#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
+#define TVE_TV_OUT_DISABLE (0x0 << 12)
+#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
+#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
+#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
+#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
+#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
+#define TVE_TV_OUT_YPBPR (0x6 << 12)
+#define TVE_TV_OUT_RGB (0x7 << 12)
+#define TVE_TV_STAND_MASK (0xf << 8)
+#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
+#define TVE_P2I_CONV_EN BIT(7)
+#define TVE_INP_VIDEO_FORM BIT(6)
+#define TVE_INP_YCBCR_422 (0x0 << 6)
+#define TVE_INP_YCBCR_444 (0x1 << 6)
+#define TVE_DATA_SOURCE_MASK (0x3 << 4)
+#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
+#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
+#define TVE_DATA_SOURCE_EXT (0x2 << 4)
+#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
+#define TVE_IPU_CLK_EN_OFS 3
+#define TVE_IPU_CLK_EN BIT(3)
+#define TVE_DAC_SAMP_RATE_OFS 1
+#define TVE_DAC_SAMP_RATE_WIDTH 2
+#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
+#define TVE_DAC_FULL_RATE (0x0 << 1)
+#define TVE_DAC_DIV2_RATE (0x1 << 1)
+#define TVE_DAC_DIV4_RATE (0x2 << 1)
+#define TVE_EN BIT(0)
+
+/* TVE_TVDACx_CONT_REG */
+#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
+
+/* TVE_CD_CONT_REG */
+#define TVE_CD_CH_2_SM_EN BIT(22)
+#define TVE_CD_CH_1_SM_EN BIT(21)
+#define TVE_CD_CH_0_SM_EN BIT(20)
+#define TVE_CD_CH_2_LM_EN BIT(18)
+#define TVE_CD_CH_1_LM_EN BIT(17)
+#define TVE_CD_CH_0_LM_EN BIT(16)
+#define TVE_CD_CH_2_REF_LVL BIT(10)
+#define TVE_CD_CH_1_REF_LVL BIT(9)
+#define TVE_CD_CH_0_REF_LVL BIT(8)
+#define TVE_CD_EN BIT(0)
+
+/* TVE_INT_CONT_REG */
+#define TVE_FRAME_END_IEN BIT(13)
+#define TVE_CD_MON_END_IEN BIT(2)
+#define TVE_CD_SM_IEN BIT(1)
+#define TVE_CD_LM_IEN BIT(0)
+
+/* TVE_TST_MODE_REG */
+#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
+
+#define IMX_TVE_DAC_VOLTAGE 2750000
+
+enum {
+ TVE_MODE_TVOUT,
+ TVE_MODE_VGA,
+};
+
+struct imx_tve_encoder {
+ struct drm_connector connector;
+ struct drm_encoder encoder;
+ struct imx_tve *tve;
+};
+
+struct imx_tve {
+ struct device *dev;
+ int mode;
+ int di_hsync_pin;
+ int di_vsync_pin;
+
+ struct regmap *regmap;
+ struct regulator *dac_reg;
+ struct i2c_adapter *ddc;
+ struct clk *clk;
+ struct clk *di_sel_clk;
+ struct clk_hw clk_hw_di;
+ struct clk *di_clk;
+};
+
+static inline struct imx_tve *con_to_tve(struct drm_connector *c)
+{
+ return container_of(c, struct imx_tve_encoder, connector)->tve;
+}
+
+static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
+{
+ return container_of(e, struct imx_tve_encoder, encoder)->tve;
+}
+
+static void tve_enable(struct imx_tve *tve)
+{
+ clk_prepare_enable(tve->clk);
+ regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
+
+ /* clear interrupt status register */
+ regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
+
+ /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
+ if (tve->mode == TVE_MODE_VGA)
+ regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
+ else
+ regmap_write(tve->regmap, TVE_INT_CONT_REG,
+ TVE_CD_SM_IEN |
+ TVE_CD_LM_IEN |
+ TVE_CD_MON_END_IEN);
+}
+
+static void tve_disable(struct imx_tve *tve)
+{
+ regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
+ clk_disable_unprepare(tve->clk);
+}
+
+static int tve_setup_tvout(struct imx_tve *tve)
+{
+ return -ENOTSUPP;
+}
+
+static int tve_setup_vga(struct imx_tve *tve)
+{
+ unsigned int mask;
+ unsigned int val;
+ int ret;
+
+ /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
+ ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
+ TVE_TVDAC_GAIN_MASK, 0x0a);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
+ TVE_TVDAC_GAIN_MASK, 0x0a);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
+ TVE_TVDAC_GAIN_MASK, 0x0a);
+ if (ret)
+ return ret;
+
+ /* set configuration register */
+ mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
+ val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
+ mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
+ val |= TVE_TV_STAND_HD_1080P30 | 0;
+ mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
+ val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
+ ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
+ if (ret)
+ return ret;
+
+ /* set test mode (as documented) */
+ return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
+ TVE_TVDAC_TEST_MODE_MASK, 1);
+}
+
+static int imx_tve_connector_get_modes(struct drm_connector *connector)
+{
+ struct imx_tve *tve = con_to_tve(connector);
+ struct edid *edid;
+ int ret = 0;
+
+ if (!tve->ddc)
+ return 0;
+
+ edid = drm_get_edid(connector, tve->ddc);
+ if (edid) {
+ drm_connector_update_edid_property(connector, edid);
+ ret = drm_add_edid_modes(connector, edid);
+ kfree(edid);
+ }
+
+ return ret;
+}
+
+static enum drm_mode_status
+imx_tve_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct imx_tve *tve = con_to_tve(connector);
+ unsigned long rate;
+
+ /* pixel clock with 2x oversampling */
+ rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
+ if (rate == mode->clock)
+ return MODE_OK;
+
+ /* pixel clock without oversampling */
+ rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
+ if (rate == mode->clock)
+ return MODE_OK;
+
+ dev_warn(tve->dev, "ignoring mode %dx%d\n",
+ mode->hdisplay, mode->vdisplay);
+
+ return MODE_BAD;
+}
+
+static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *orig_mode,
+ struct drm_display_mode *mode)
+{
+ struct imx_tve *tve = enc_to_tve(encoder);
+ unsigned long rounded_rate;
+ unsigned long rate;
+ int div = 1;
+ int ret;
+
+ /*
+ * FIXME
+ * we should try 4k * mode->clock first,
+ * and enable 4x oversampling for lower resolutions
+ */
+ rate = 2000UL * mode->clock;
+ clk_set_rate(tve->clk, rate);
+ rounded_rate = clk_get_rate(tve->clk);
+ if (rounded_rate >= rate)
+ div = 2;
+ clk_set_rate(tve->di_clk, rounded_rate / div);
+
+ ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
+ if (ret < 0) {
+ dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
+ ret);
+ }
+
+ regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
+ TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
+
+ if (tve->mode == TVE_MODE_VGA)
+ ret = tve_setup_vga(tve);
+ else
+ ret = tve_setup_tvout(tve);
+ if (ret)
+ dev_err(tve->dev, "failed to set configuration: %d\n", ret);
+}
+
+static void imx_tve_encoder_enable(struct drm_encoder *encoder)
+{
+ struct imx_tve *tve = enc_to_tve(encoder);
+
+ tve_enable(tve);
+}
+
+static void imx_tve_encoder_disable(struct drm_encoder *encoder)
+{
+ struct imx_tve *tve = enc_to_tve(encoder);
+
+ tve_disable(tve);
+}
+
+static int imx_tve_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
+ struct imx_tve *tve = enc_to_tve(encoder);
+
+ imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
+ imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
+ imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
+
+ return 0;
+}
+
+static const struct drm_connector_funcs imx_tve_connector_funcs = {
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = imx_drm_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
+ .get_modes = imx_tve_connector_get_modes,
+ .mode_valid = imx_tve_connector_mode_valid,
+};
+
+static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
+ .mode_set = imx_tve_encoder_mode_set,
+ .enable = imx_tve_encoder_enable,
+ .disable = imx_tve_encoder_disable,
+ .atomic_check = imx_tve_atomic_check,
+};
+
+static irqreturn_t imx_tve_irq_handler(int irq, void *data)
+{
+ struct imx_tve *tve = data;
+ unsigned int val;
+
+ regmap_read(tve->regmap, TVE_STAT_REG, &val);
+
+ /* clear interrupt status register */
+ regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
+
+ return IRQ_HANDLED;
+}
+
+static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
+ if (ret < 0)
+ return 0;
+
+ switch (val & TVE_DAC_SAMP_RATE_MASK) {
+ case TVE_DAC_DIV4_RATE:
+ return parent_rate / 4;
+ case TVE_DAC_DIV2_RATE:
+ return parent_rate / 2;
+ case TVE_DAC_FULL_RATE:
+ default:
+ return parent_rate;
+ }
+
+ return 0;
+}
+
+static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long div;
+
+ div = *prate / rate;
+ if (div >= 4)
+ return *prate / 4;
+ else if (div >= 2)
+ return *prate / 2;
+ return *prate;
+}
+
+static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
+ unsigned long div;
+ u32 val;
+ int ret;
+
+ div = parent_rate / rate;
+ if (div >= 4)
+ val = TVE_DAC_DIV4_RATE;
+ else if (div >= 2)
+ val = TVE_DAC_DIV2_RATE;
+ else
+ val = TVE_DAC_FULL_RATE;
+
+ ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
+ TVE_DAC_SAMP_RATE_MASK, val);
+
+ if (ret < 0) {
+ dev_err(tve->dev, "failed to set divider: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct clk_ops clk_tve_di_ops = {
+ .round_rate = clk_tve_di_round_rate,
+ .set_rate = clk_tve_di_set_rate,
+ .recalc_rate = clk_tve_di_recalc_rate,
+};
+
+static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
+{
+ const char *tve_di_parent[1];
+ struct clk_init_data init = {
+ .name = "tve_di",
+ .ops = &clk_tve_di_ops,
+ .num_parents = 1,
+ .flags = 0,
+ };
+
+ tve_di_parent[0] = __clk_get_name(tve->clk);
+ init.parent_names = (const char **)&tve_di_parent;
+
+ tve->clk_hw_di.init = &init;
+ tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di);
+ if (IS_ERR(tve->di_clk)) {
+ dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
+ PTR_ERR(tve->di_clk));
+ return PTR_ERR(tve->di_clk);
+ }
+
+ return 0;
+}
+
+static void imx_tve_disable_regulator(void *data)
+{
+ struct imx_tve *tve = data;
+
+ regulator_disable(tve->dac_reg);
+}
+
+static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
+{
+ return (reg % 4 == 0) && (reg <= 0xdc);
+}
+
+static struct regmap_config tve_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+
+ .readable_reg = imx_tve_readable_reg,
+
+ .fast_io = true,
+
+ .max_register = 0xdc,
+};
+
+static const char * const imx_tve_modes[] = {
+ [TVE_MODE_TVOUT] = "tvout",
+ [TVE_MODE_VGA] = "vga",
+};
+
+static int of_get_tve_mode(struct device_node *np)
+{
+ const char *bm;
+ int ret, i;
+
+ ret = of_property_read_string(np, "fsl,tve-mode", &bm);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
+ if (!strcasecmp(bm, imx_tve_modes[i]))
+ return i;
+
+ return -EINVAL;
+}
+
+static int imx_tve_bind(struct device *dev, struct device *master, void *data)
+{
+ struct drm_device *drm = data;
+ struct imx_tve *tve = dev_get_drvdata(dev);
+ struct imx_tve_encoder *tvee;
+ struct drm_encoder *encoder;
+ struct drm_connector *connector;
+ int encoder_type;
+ int ret;
+
+ encoder_type = tve->mode == TVE_MODE_VGA ?
+ DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
+
+ tvee = drmm_simple_encoder_alloc(drm, struct imx_tve_encoder, encoder,
+ encoder_type);
+ if (IS_ERR(tvee))
+ return PTR_ERR(tvee);
+
+ tvee->tve = tve;
+ encoder = &tvee->encoder;
+ connector = &tvee->connector;
+
+ ret = imx_drm_encoder_parse_of(drm, encoder, tve->dev->of_node);
+ if (ret)
+ return ret;
+
+ drm_encoder_helper_add(encoder, &imx_tve_encoder_helper_funcs);
+
+ drm_connector_helper_add(connector, &imx_tve_connector_helper_funcs);
+ ret = drm_connector_init_with_ddc(drm, connector,
+ &imx_tve_connector_funcs,
+ DRM_MODE_CONNECTOR_VGA, tve->ddc);
+ if (ret)
+ return ret;
+
+ return drm_connector_attach_encoder(connector, encoder);
+}
+
+static const struct component_ops imx_tve_ops = {
+ .bind = imx_tve_bind,
+};
+
+static int imx_tve_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *ddc_node;
+ struct imx_tve *tve;
+ void __iomem *base;
+ unsigned int val;
+ int irq;
+ int ret;
+
+ tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
+ if (!tve)
+ return -ENOMEM;
+
+ tve->dev = dev;
+
+ ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
+ if (ddc_node) {
+ tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
+ of_node_put(ddc_node);
+ }
+
+ tve->mode = of_get_tve_mode(np);
+ if (tve->mode != TVE_MODE_VGA) {
+ dev_err(dev, "only VGA mode supported, currently\n");
+ return -EINVAL;
+ }
+
+ if (tve->mode == TVE_MODE_VGA) {
+ ret = of_property_read_u32(np, "fsl,hsync-pin",
+ &tve->di_hsync_pin);
+
+ if (ret < 0) {
+ dev_err(dev, "failed to get hsync pin\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(np, "fsl,vsync-pin",
+ &tve->di_vsync_pin);
+
+ if (ret < 0) {
+ dev_err(dev, "failed to get vsync pin\n");
+ return ret;
+ }
+ }
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ tve_regmap_config.lock_arg = tve;
+ tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
+ &tve_regmap_config);
+ if (IS_ERR(tve->regmap)) {
+ dev_err(dev, "failed to init regmap: %ld\n",
+ PTR_ERR(tve->regmap));
+ return PTR_ERR(tve->regmap);
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_threaded_irq(dev, irq, NULL,
+ imx_tve_irq_handler, IRQF_ONESHOT,
+ "imx-tve", tve);
+ if (ret < 0) {
+ dev_err(dev, "failed to request irq: %d\n", ret);
+ return ret;
+ }
+
+ tve->dac_reg = devm_regulator_get(dev, "dac");
+ if (!IS_ERR(tve->dac_reg)) {
+ if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
+ dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
+ ret = regulator_enable(tve->dac_reg);
+ if (ret)
+ return ret;
+ ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
+ if (ret)
+ return ret;
+ }
+
+ tve->clk = devm_clk_get(dev, "tve");
+ if (IS_ERR(tve->clk)) {
+ dev_err(dev, "failed to get high speed tve clock: %ld\n",
+ PTR_ERR(tve->clk));
+ return PTR_ERR(tve->clk);
+ }
+
+ /* this is the IPU DI clock input selector, can be parented to tve_di */
+ tve->di_sel_clk = devm_clk_get(dev, "di_sel");
+ if (IS_ERR(tve->di_sel_clk)) {
+ dev_err(dev, "failed to get ipu di mux clock: %ld\n",
+ PTR_ERR(tve->di_sel_clk));
+ return PTR_ERR(tve->di_sel_clk);
+ }
+
+ ret = tve_clk_init(tve, base);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
+ if (ret < 0) {
+ dev_err(dev, "failed to read configuration register: %d\n",
+ ret);
+ return ret;
+ }
+ if (val != 0x00100000) {
+ dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
+ return -ENODEV;
+ }
+
+ /* disable cable detection for VGA mode */
+ ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, tve);
+
+ return component_add(dev, &imx_tve_ops);
+}
+
+static int imx_tve_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &imx_tve_ops);
+ return 0;
+}
+
+static const struct of_device_id imx_tve_dt_ids[] = {
+ { .compatible = "fsl,imx53-tve", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
+
+static struct platform_driver imx_tve_driver = {
+ .probe = imx_tve_probe,
+ .remove = imx_tve_remove,
+ .driver = {
+ .of_match_table = imx_tve_dt_ids,
+ .name = "imx-tve",
+ },
+};
+
+module_platform_driver(imx_tve_driver);
+
+MODULE_DESCRIPTION("i.MX Television Encoder driver");
+MODULE_AUTHOR("Philipp Zabel, Pengutronix");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:imx-tve");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX IPUv3 Graphics driver
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <video/imx-ipu-v3.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "imx-drm.h"
+#include "ipuv3-plane.h"
+
+#define DRIVER_DESC "i.MX IPUv3 Graphics"
+
+struct ipu_crtc {
+ struct device *dev;
+ struct drm_crtc base;
+
+ /* plane[0] is the full plane, plane[1] is the partial plane */
+ struct ipu_plane *plane[2];
+
+ struct ipu_dc *dc;
+ struct ipu_di *di;
+ int irq;
+ struct drm_pending_vblank_event *event;
+};
+
+static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
+{
+ return container_of(crtc, struct ipu_crtc, base);
+}
+
+static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+ struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
+
+ ipu_prg_enable(ipu);
+ ipu_dc_enable(ipu);
+ ipu_dc_enable_channel(ipu_crtc->dc);
+ ipu_di_enable(ipu_crtc->di);
+}
+
+static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ bool disable_partial = false;
+ bool disable_full = false;
+ struct drm_plane *plane;
+
+ drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
+ if (plane == &ipu_crtc->plane[0]->base)
+ disable_full = true;
+ if (ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
+ disable_partial = true;
+ }
+
+ if (disable_partial)
+ ipu_plane_disable(ipu_crtc->plane[1], true);
+ if (disable_full)
+ ipu_plane_disable(ipu_crtc->plane[0], true);
+}
+
+static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
+ crtc);
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+ struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
+
+ ipu_dc_disable_channel(ipu_crtc->dc);
+ ipu_di_disable(ipu_crtc->di);
+ /*
+ * Planes must be disabled before DC clock is removed, as otherwise the
+ * attached IDMACs will be left in undefined state, possibly hanging
+ * the IPU or even system.
+ */
+ ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
+ ipu_dc_disable(ipu);
+ ipu_prg_disable(ipu);
+
+ drm_crtc_vblank_off(crtc);
+
+ spin_lock_irq(&crtc->dev->event_lock);
+ if (crtc->state->event && !crtc->state->active) {
+ drm_crtc_send_vblank_event(crtc, crtc->state->event);
+ crtc->state->event = NULL;
+ }
+ spin_unlock_irq(&crtc->dev->event_lock);
+}
+
+static void imx_drm_crtc_reset(struct drm_crtc *crtc)
+{
+ struct imx_crtc_state *state;
+
+ if (crtc->state)
+ __drm_atomic_helper_crtc_destroy_state(crtc->state);
+
+ kfree(to_imx_crtc_state(crtc->state));
+ crtc->state = NULL;
+
+ state = kzalloc(sizeof(*state), GFP_KERNEL);
+ if (state)
+ __drm_atomic_helper_crtc_reset(crtc, &state->base);
+}
+
+static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
+{
+ struct imx_crtc_state *state;
+
+ state = kzalloc(sizeof(*state), GFP_KERNEL);
+ if (!state)
+ return NULL;
+
+ __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
+
+ WARN_ON(state->base.crtc != crtc);
+ state->base.crtc = crtc;
+
+ return &state->base;
+}
+
+static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
+{
+ __drm_atomic_helper_crtc_destroy_state(state);
+ kfree(to_imx_crtc_state(state));
+}
+
+static int ipu_enable_vblank(struct drm_crtc *crtc)
+{
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+
+ enable_irq(ipu_crtc->irq);
+
+ return 0;
+}
+
+static void ipu_disable_vblank(struct drm_crtc *crtc)
+{
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+
+ disable_irq_nosync(ipu_crtc->irq);
+}
+
+static const struct drm_crtc_funcs ipu_crtc_funcs = {
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .reset = imx_drm_crtc_reset,
+ .atomic_duplicate_state = imx_drm_crtc_duplicate_state,
+ .atomic_destroy_state = imx_drm_crtc_destroy_state,
+ .enable_vblank = ipu_enable_vblank,
+ .disable_vblank = ipu_disable_vblank,
+};
+
+static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
+{
+ struct ipu_crtc *ipu_crtc = dev_id;
+ struct drm_crtc *crtc = &ipu_crtc->base;
+ unsigned long flags;
+ int i;
+
+ drm_crtc_handle_vblank(crtc);
+
+ if (ipu_crtc->event) {
+ for (i = 0; i < ARRAY_SIZE(ipu_crtc->plane); i++) {
+ struct ipu_plane *plane = ipu_crtc->plane[i];
+
+ if (!plane)
+ continue;
+
+ if (ipu_plane_atomic_update_pending(&plane->base))
+ break;
+ }
+
+ if (i == ARRAY_SIZE(ipu_crtc->plane)) {
+ spin_lock_irqsave(&crtc->dev->event_lock, flags);
+ drm_crtc_send_vblank_event(crtc, ipu_crtc->event);
+ ipu_crtc->event = NULL;
+ drm_crtc_vblank_put(crtc);
+ spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+ struct videomode vm;
+ int ret;
+
+ drm_display_mode_to_videomode(adjusted_mode, &vm);
+
+ ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
+ if (ret)
+ return false;
+
+ if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
+ return false;
+
+ drm_display_mode_from_videomode(&vm, adjusted_mode);
+
+ return true;
+}
+
+static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
+ crtc);
+ u32 primary_plane_mask = drm_plane_mask(crtc->primary);
+
+ if (crtc_state->active && (primary_plane_mask & crtc_state->plane_mask) == 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+ drm_crtc_vblank_on(crtc);
+}
+
+static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+ spin_lock_irq(&crtc->dev->event_lock);
+ if (crtc->state->event) {
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+
+ WARN_ON(drm_crtc_vblank_get(crtc));
+ ipu_crtc->event = crtc->state->event;
+ crtc->state->event = NULL;
+ }
+ spin_unlock_irq(&crtc->dev->event_lock);
+}
+
+static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_encoder *encoder;
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
+ struct ipu_di_signal_cfg sig_cfg = {};
+ unsigned long encoder_types = 0;
+
+ dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
+ mode->hdisplay);
+ dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
+ mode->vdisplay);
+
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ if (encoder->crtc == crtc)
+ encoder_types |= BIT(encoder->encoder_type);
+ }
+
+ dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
+ __func__, encoder_types);
+
+ /*
+ * If we have DAC or LDB, then we need the IPU DI clock to be
+ * the same as the LDB DI clock. For TVDAC, derive the IPU DI
+ * clock from 27 MHz TVE_DI clock, but allow to divide it.
+ */
+ if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
+ BIT(DRM_MODE_ENCODER_LVDS)))
+ sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
+ else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
+ sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
+ else
+ sig_cfg.clkflags = 0;
+
+ sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
+ /* Default to driving pixel data on negative clock edges */
+ sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
+ DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE);
+ sig_cfg.bus_format = imx_crtc_state->bus_format;
+ sig_cfg.v_to_h_sync = 0;
+ sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
+ sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
+
+ drm_display_mode_to_videomode(mode, &sig_cfg.mode);
+ if (!IS_ALIGNED(sig_cfg.mode.hactive, 8)) {
+ unsigned int new_hactive = ALIGN(sig_cfg.mode.hactive, 8);
+
+ dev_warn(ipu_crtc->dev, "8-pixel align hactive %d -> %d\n",
+ sig_cfg.mode.hactive, new_hactive);
+
+ sig_cfg.mode.hfront_porch = new_hactive - sig_cfg.mode.hactive;
+ sig_cfg.mode.hactive = new_hactive;
+ }
+
+ ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
+ mode->flags & DRM_MODE_FLAG_INTERLACE,
+ imx_crtc_state->bus_format, sig_cfg.mode.hactive);
+ ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
+}
+
+static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
+ .mode_fixup = ipu_crtc_mode_fixup,
+ .mode_set_nofb = ipu_crtc_mode_set_nofb,
+ .atomic_check = ipu_crtc_atomic_check,
+ .atomic_begin = ipu_crtc_atomic_begin,
+ .atomic_flush = ipu_crtc_atomic_flush,
+ .atomic_disable = ipu_crtc_atomic_disable,
+ .atomic_enable = ipu_crtc_atomic_enable,
+};
+
+static void ipu_put_resources(struct drm_device *dev, void *ptr)
+{
+ struct ipu_crtc *ipu_crtc = ptr;
+
+ if (!IS_ERR_OR_NULL(ipu_crtc->dc))
+ ipu_dc_put(ipu_crtc->dc);
+ if (!IS_ERR_OR_NULL(ipu_crtc->di))
+ ipu_di_put(ipu_crtc->di);
+}
+
+static int ipu_get_resources(struct drm_device *dev, struct ipu_crtc *ipu_crtc,
+ struct ipu_client_platformdata *pdata)
+{
+ struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
+ int ret;
+
+ ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
+ if (IS_ERR(ipu_crtc->dc))
+ return PTR_ERR(ipu_crtc->dc);
+
+ ret = drmm_add_action_or_reset(dev, ipu_put_resources, ipu_crtc);
+ if (ret)
+ return ret;
+
+ ipu_crtc->di = ipu_di_get(ipu, pdata->di);
+ if (IS_ERR(ipu_crtc->di))
+ return PTR_ERR(ipu_crtc->di);
+
+ return 0;
+}
+
+static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
+{
+ struct ipu_client_platformdata *pdata = dev->platform_data;
+ struct ipu_soc *ipu = dev_get_drvdata(dev->parent);
+ struct drm_device *drm = data;
+ struct ipu_plane *primary_plane;
+ struct ipu_crtc *ipu_crtc;
+ struct drm_crtc *crtc;
+ int dp = -EINVAL;
+ int ret;
+
+ if (pdata->dp >= 0)
+ dp = IPU_DP_FLOW_SYNC_BG;
+ primary_plane = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
+ DRM_PLANE_TYPE_PRIMARY);
+ if (IS_ERR(primary_plane))
+ return PTR_ERR(primary_plane);
+
+ ipu_crtc = drmm_crtc_alloc_with_planes(drm, struct ipu_crtc, base,
+ &primary_plane->base, NULL,
+ &ipu_crtc_funcs, NULL);
+ if (IS_ERR(ipu_crtc))
+ return PTR_ERR(ipu_crtc);
+
+ ipu_crtc->dev = dev;
+ ipu_crtc->plane[0] = primary_plane;
+
+ crtc = &ipu_crtc->base;
+ crtc->port = pdata->of_node;
+ drm_crtc_helper_add(crtc, &ipu_helper_funcs);
+
+ ret = ipu_get_resources(drm, ipu_crtc, pdata);
+ if (ret) {
+ dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
+ ret);
+ return ret;
+ }
+
+ /* If this crtc is using the DP, add an overlay plane */
+ if (pdata->dp >= 0 && pdata->dma[1] > 0) {
+ ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
+ IPU_DP_FLOW_SYNC_FG,
+ drm_crtc_mask(&ipu_crtc->base),
+ DRM_PLANE_TYPE_OVERLAY);
+ if (IS_ERR(ipu_crtc->plane[1]))
+ ipu_crtc->plane[1] = NULL;
+ }
+
+ ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
+ ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
+ "imx_drm", ipu_crtc);
+ if (ret < 0) {
+ dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
+ return ret;
+ }
+ /* Only enable IRQ when we actually need it to trigger work. */
+ disable_irq(ipu_crtc->irq);
+
+ return 0;
+}
+
+static const struct component_ops ipu_crtc_ops = {
+ .bind = ipu_drm_bind,
+};
+
+static int ipu_drm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ if (!dev->platform_data)
+ return -EINVAL;
+
+ ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+ if (ret)
+ return ret;
+
+ return component_add(dev, &ipu_crtc_ops);
+}
+
+static int ipu_drm_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &ipu_crtc_ops);
+ return 0;
+}
+
+struct platform_driver ipu_drm_driver = {
+ .driver = {
+ .name = "imx-ipuv3-crtc",
+ },
+ .probe = ipu_drm_probe,
+ .remove = ipu_drm_remove,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX IPUv3 DP Overlay Planes
+ *
+ * Copyright (C) 2013 Philipp Zabel, Pengutronix
+ */
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_blend.h>
+#include <drm/drm_fb_dma_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_gem_atomic_helper.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_managed.h>
+
+#include <video/imx-ipu-v3.h>
+
+#include "imx-drm.h"
+#include "ipuv3-plane.h"
+
+struct ipu_plane_state {
+ struct drm_plane_state base;
+ bool use_pre;
+};
+
+static inline struct ipu_plane_state *
+to_ipu_plane_state(struct drm_plane_state *p)
+{
+ return container_of(p, struct ipu_plane_state, base);
+}
+
+static unsigned int ipu_src_rect_width(const struct drm_plane_state *state)
+{
+ return ALIGN(drm_rect_width(&state->src) >> 16, 8);
+}
+
+static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
+{
+ return container_of(p, struct ipu_plane, base);
+}
+
+static const uint32_t ipu_plane_all_formats[] = {
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ABGR1555,
+ DRM_FORMAT_XBGR1555,
+ DRM_FORMAT_RGBA5551,
+ DRM_FORMAT_BGRA5551,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+ DRM_FORMAT_YUV422,
+ DRM_FORMAT_YVU422,
+ DRM_FORMAT_YUV444,
+ DRM_FORMAT_YVU444,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_RGB565_A8,
+ DRM_FORMAT_BGR565_A8,
+ DRM_FORMAT_RGB888_A8,
+ DRM_FORMAT_BGR888_A8,
+ DRM_FORMAT_RGBX8888_A8,
+ DRM_FORMAT_BGRX8888_A8,
+};
+
+static const uint32_t ipu_plane_rgb_formats[] = {
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ABGR1555,
+ DRM_FORMAT_XBGR1555,
+ DRM_FORMAT_RGBA5551,
+ DRM_FORMAT_BGRA5551,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_RGB565_A8,
+ DRM_FORMAT_BGR565_A8,
+ DRM_FORMAT_RGB888_A8,
+ DRM_FORMAT_BGR888_A8,
+ DRM_FORMAT_RGBX8888_A8,
+ DRM_FORMAT_BGRX8888_A8,
+};
+
+static const uint64_t ipu_format_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static const uint64_t pre_format_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_VIVANTE_TILED,
+ DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
+ DRM_FORMAT_MOD_INVALID
+};
+
+int ipu_plane_irq(struct ipu_plane *ipu_plane)
+{
+ return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
+ IPU_IRQ_EOF);
+}
+
+static inline unsigned long
+drm_plane_state_to_eba(struct drm_plane_state *state, int plane)
+{
+ struct drm_framebuffer *fb = state->fb;
+ struct drm_gem_dma_object *dma_obj;
+ int x = state->src.x1 >> 16;
+ int y = state->src.y1 >> 16;
+
+ dma_obj = drm_fb_dma_get_gem_obj(fb, plane);
+ BUG_ON(!dma_obj);
+
+ return dma_obj->dma_addr + fb->offsets[plane] + fb->pitches[plane] * y +
+ fb->format->cpp[plane] * x;
+}
+
+static inline unsigned long
+drm_plane_state_to_ubo(struct drm_plane_state *state)
+{
+ struct drm_framebuffer *fb = state->fb;
+ struct drm_gem_dma_object *dma_obj;
+ unsigned long eba = drm_plane_state_to_eba(state, 0);
+ int x = state->src.x1 >> 16;
+ int y = state->src.y1 >> 16;
+
+ dma_obj = drm_fb_dma_get_gem_obj(fb, 1);
+ BUG_ON(!dma_obj);
+
+ x /= fb->format->hsub;
+ y /= fb->format->vsub;
+
+ return dma_obj->dma_addr + fb->offsets[1] + fb->pitches[1] * y +
+ fb->format->cpp[1] * x - eba;
+}
+
+static inline unsigned long
+drm_plane_state_to_vbo(struct drm_plane_state *state)
+{
+ struct drm_framebuffer *fb = state->fb;
+ struct drm_gem_dma_object *dma_obj;
+ unsigned long eba = drm_plane_state_to_eba(state, 0);
+ int x = state->src.x1 >> 16;
+ int y = state->src.y1 >> 16;
+
+ dma_obj = drm_fb_dma_get_gem_obj(fb, 2);
+ BUG_ON(!dma_obj);
+
+ x /= fb->format->hsub;
+ y /= fb->format->vsub;
+
+ return dma_obj->dma_addr + fb->offsets[2] + fb->pitches[2] * y +
+ fb->format->cpp[2] * x - eba;
+}
+
+static void ipu_plane_put_resources(struct drm_device *dev, void *ptr)
+{
+ struct ipu_plane *ipu_plane = ptr;
+
+ if (!IS_ERR_OR_NULL(ipu_plane->dp))
+ ipu_dp_put(ipu_plane->dp);
+ if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
+ ipu_dmfc_put(ipu_plane->dmfc);
+ if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
+ ipu_idmac_put(ipu_plane->ipu_ch);
+ if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch))
+ ipu_idmac_put(ipu_plane->alpha_ch);
+}
+
+static int ipu_plane_get_resources(struct drm_device *dev,
+ struct ipu_plane *ipu_plane)
+{
+ int ret;
+ int alpha_ch;
+
+ ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
+ if (IS_ERR(ipu_plane->ipu_ch)) {
+ ret = PTR_ERR(ipu_plane->ipu_ch);
+ DRM_ERROR("failed to get idmac channel: %d\n", ret);
+ return ret;
+ }
+
+ ret = drmm_add_action_or_reset(dev, ipu_plane_put_resources, ipu_plane);
+ if (ret)
+ return ret;
+
+ alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma);
+ if (alpha_ch >= 0) {
+ ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch);
+ if (IS_ERR(ipu_plane->alpha_ch)) {
+ ret = PTR_ERR(ipu_plane->alpha_ch);
+ DRM_ERROR("failed to get alpha idmac channel %d: %d\n",
+ alpha_ch, ret);
+ return ret;
+ }
+ }
+
+ ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
+ if (IS_ERR(ipu_plane->dmfc)) {
+ ret = PTR_ERR(ipu_plane->dmfc);
+ DRM_ERROR("failed to get dmfc: ret %d\n", ret);
+ return ret;
+ }
+
+ if (ipu_plane->dp_flow >= 0) {
+ ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
+ if (IS_ERR(ipu_plane->dp)) {
+ ret = PTR_ERR(ipu_plane->dp);
+ DRM_ERROR("failed to get dp flow: %d\n", ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane)
+{
+ switch (ipu_plane->base.state->fb->format->format) {
+ case DRM_FORMAT_RGB565_A8:
+ case DRM_FORMAT_BGR565_A8:
+ case DRM_FORMAT_RGB888_A8:
+ case DRM_FORMAT_BGR888_A8:
+ case DRM_FORMAT_RGBX8888_A8:
+ case DRM_FORMAT_BGRX8888_A8:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static void ipu_plane_enable(struct ipu_plane *ipu_plane)
+{
+ if (ipu_plane->dp)
+ ipu_dp_enable(ipu_plane->ipu);
+ ipu_dmfc_enable_channel(ipu_plane->dmfc);
+ ipu_idmac_enable_channel(ipu_plane->ipu_ch);
+ if (ipu_plane_separate_alpha(ipu_plane))
+ ipu_idmac_enable_channel(ipu_plane->alpha_ch);
+ if (ipu_plane->dp)
+ ipu_dp_enable_channel(ipu_plane->dp);
+}
+
+void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel)
+{
+ int ret;
+
+ DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
+
+ ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
+ if (ret == -ETIMEDOUT) {
+ DRM_ERROR("[PLANE:%d] IDMAC timeout\n",
+ ipu_plane->base.base.id);
+ }
+
+ if (ipu_plane->dp && disable_dp_channel)
+ ipu_dp_disable_channel(ipu_plane->dp, false);
+ ipu_idmac_disable_channel(ipu_plane->ipu_ch);
+ if (ipu_plane->alpha_ch)
+ ipu_idmac_disable_channel(ipu_plane->alpha_ch);
+ ipu_dmfc_disable_channel(ipu_plane->dmfc);
+ if (ipu_plane->dp)
+ ipu_dp_disable(ipu_plane->ipu);
+ if (ipu_prg_present(ipu_plane->ipu))
+ ipu_prg_channel_disable(ipu_plane->ipu_ch);
+}
+
+void ipu_plane_disable_deferred(struct drm_plane *plane)
+{
+ struct ipu_plane *ipu_plane = to_ipu_plane(plane);
+
+ if (ipu_plane->disabling) {
+ ipu_plane->disabling = false;
+ ipu_plane_disable(ipu_plane, false);
+ }
+}
+
+static void ipu_plane_state_reset(struct drm_plane *plane)
+{
+ struct ipu_plane_state *ipu_state;
+
+ if (plane->state) {
+ ipu_state = to_ipu_plane_state(plane->state);
+ __drm_atomic_helper_plane_destroy_state(plane->state);
+ kfree(ipu_state);
+ plane->state = NULL;
+ }
+
+ ipu_state = kzalloc(sizeof(*ipu_state), GFP_KERNEL);
+
+ if (ipu_state)
+ __drm_atomic_helper_plane_reset(plane, &ipu_state->base);
+}
+
+static struct drm_plane_state *
+ipu_plane_duplicate_state(struct drm_plane *plane)
+{
+ struct ipu_plane_state *state;
+
+ if (WARN_ON(!plane->state))
+ return NULL;
+
+ state = kmalloc(sizeof(*state), GFP_KERNEL);
+ if (state)
+ __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
+
+ return &state->base;
+}
+
+static void ipu_plane_destroy_state(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
+
+ __drm_atomic_helper_plane_destroy_state(state);
+ kfree(ipu_state);
+}
+
+static bool ipu_plane_format_mod_supported(struct drm_plane *plane,
+ uint32_t format, uint64_t modifier)
+{
+ struct ipu_soc *ipu = to_ipu_plane(plane)->ipu;
+
+ /* linear is supported for all planes and formats */
+ if (modifier == DRM_FORMAT_MOD_LINEAR)
+ return true;
+
+ /*
+ * Without a PRG the possible modifiers list only includes the linear
+ * modifier, so we always take the early return from this function and
+ * only end up here if the PRG is present.
+ */
+ return ipu_prg_format_supported(ipu, format, modifier);
+}
+
+static const struct drm_plane_funcs ipu_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .reset = ipu_plane_state_reset,
+ .atomic_duplicate_state = ipu_plane_duplicate_state,
+ .atomic_destroy_state = ipu_plane_destroy_state,
+ .format_mod_supported = ipu_plane_format_mod_supported,
+};
+
+static int ipu_plane_atomic_check(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+ plane);
+ struct drm_crtc_state *crtc_state;
+ struct device *dev = plane->dev->dev;
+ struct drm_framebuffer *fb = new_state->fb;
+ struct drm_framebuffer *old_fb = old_state->fb;
+ unsigned long eba, ubo, vbo, old_ubo, old_vbo, alpha_eba;
+ bool can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
+ int ret;
+
+ /* Ok to disable */
+ if (!fb)
+ return 0;
+
+ if (WARN_ON(!new_state->crtc))
+ return -EINVAL;
+
+ crtc_state =
+ drm_atomic_get_existing_crtc_state(state,
+ new_state->crtc);
+ if (WARN_ON(!crtc_state))
+ return -EINVAL;
+
+ ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ can_position, true);
+ if (ret)
+ return ret;
+
+ /* nothing to check when disabling or disabled */
+ if (!crtc_state->enable)
+ return 0;
+
+ switch (plane->type) {
+ case DRM_PLANE_TYPE_PRIMARY:
+ /* full plane minimum width is 13 pixels */
+ if (drm_rect_width(&new_state->dst) < 13)
+ return -EINVAL;
+ break;
+ case DRM_PLANE_TYPE_OVERLAY:
+ break;
+ default:
+ dev_warn(dev, "Unsupported plane type %d\n", plane->type);
+ return -EINVAL;
+ }
+
+ if (drm_rect_height(&new_state->dst) < 2)
+ return -EINVAL;
+
+ /*
+ * We support resizing active plane or changing its format by
+ * forcing CRTC mode change in plane's ->atomic_check callback
+ * and disabling all affected active planes in CRTC's ->atomic_disable
+ * callback. The planes will be reenabled in plane's ->atomic_update
+ * callback.
+ */
+ if (old_fb &&
+ (drm_rect_width(&new_state->dst) != drm_rect_width(&old_state->dst) ||
+ drm_rect_height(&new_state->dst) != drm_rect_height(&old_state->dst) ||
+ fb->format != old_fb->format))
+ crtc_state->mode_changed = true;
+
+ eba = drm_plane_state_to_eba(new_state, 0);
+
+ if (eba & 0x7)
+ return -EINVAL;
+
+ if (fb->pitches[0] < 1 || fb->pitches[0] > 16384)
+ return -EINVAL;
+
+ if (old_fb && fb->pitches[0] != old_fb->pitches[0])
+ crtc_state->mode_changed = true;
+
+ if (ALIGN(fb->width, 8) * fb->format->cpp[0] >
+ fb->pitches[0] + fb->offsets[0]) {
+ dev_warn(dev, "pitch is not big enough for 8 pixels alignment");
+ return -EINVAL;
+ }
+
+ switch (fb->format->format) {
+ case DRM_FORMAT_YUV420:
+ case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YUV444:
+ case DRM_FORMAT_YVU444:
+ /*
+ * Multiplanar formats have to meet the following restrictions:
+ * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
+ * - EBA, UBO and VBO are a multiple of 8
+ * - UBO and VBO are unsigned and not larger than 0xfffff8
+ * - Only EBA may be changed while scanout is active
+ * - The strides of U and V planes must be identical.
+ */
+ vbo = drm_plane_state_to_vbo(new_state);
+
+ if (vbo & 0x7 || vbo > 0xfffff8)
+ return -EINVAL;
+
+ if (old_fb && (fb->format == old_fb->format)) {
+ old_vbo = drm_plane_state_to_vbo(old_state);
+ if (vbo != old_vbo)
+ crtc_state->mode_changed = true;
+ }
+
+ if (fb->pitches[1] != fb->pitches[2])
+ return -EINVAL;
+
+ fallthrough;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV16:
+ ubo = drm_plane_state_to_ubo(new_state);
+
+ if (ubo & 0x7 || ubo > 0xfffff8)
+ return -EINVAL;
+
+ if (old_fb && (fb->format == old_fb->format)) {
+ old_ubo = drm_plane_state_to_ubo(old_state);
+ if (ubo != old_ubo)
+ crtc_state->mode_changed = true;
+ }
+
+ if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
+ return -EINVAL;
+
+ if (old_fb && old_fb->pitches[1] != fb->pitches[1])
+ crtc_state->mode_changed = true;
+
+ /*
+ * The x/y offsets must be even in case of horizontal/vertical
+ * chroma subsampling.
+ */
+ if (((new_state->src.x1 >> 16) & (fb->format->hsub - 1)) ||
+ ((new_state->src.y1 >> 16) & (fb->format->vsub - 1)))
+ return -EINVAL;
+ break;
+ case DRM_FORMAT_RGB565_A8:
+ case DRM_FORMAT_BGR565_A8:
+ case DRM_FORMAT_RGB888_A8:
+ case DRM_FORMAT_BGR888_A8:
+ case DRM_FORMAT_RGBX8888_A8:
+ case DRM_FORMAT_BGRX8888_A8:
+ alpha_eba = drm_plane_state_to_eba(new_state, 1);
+ if (alpha_eba & 0x7)
+ return -EINVAL;
+
+ if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
+ return -EINVAL;
+
+ if (old_fb && old_fb->pitches[1] != fb->pitches[1])
+ crtc_state->mode_changed = true;
+ break;
+ }
+
+ return 0;
+}
+
+static void ipu_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+ struct ipu_plane *ipu_plane = to_ipu_plane(plane);
+
+ if (ipu_plane->dp)
+ ipu_dp_disable_channel(ipu_plane->dp, true);
+ ipu_plane->disabling = true;
+}
+
+static int ipu_chan_assign_axi_id(int ipu_chan)
+{
+ switch (ipu_chan) {
+ case IPUV3_CHANNEL_MEM_BG_SYNC:
+ return 1;
+ case IPUV3_CHANNEL_MEM_FG_SYNC:
+ return 2;
+ case IPUV3_CHANNEL_MEM_DC_SYNC:
+ return 3;
+ default:
+ return 0;
+ }
+}
+
+static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride,
+ u8 *burstsize, u8 *num_bursts)
+{
+ const unsigned int width_bytes = width * cpp;
+ unsigned int npb, bursts;
+
+ /* Maximum number of pixels per burst without overshooting stride */
+ for (npb = 64 / cpp; npb > 0; --npb) {
+ if (round_up(width_bytes, npb * cpp) <= stride)
+ break;
+ }
+ *burstsize = npb;
+
+ /* Maximum number of consecutive bursts without overshooting stride */
+ for (bursts = 8; bursts > 1; bursts /= 2) {
+ if (round_up(width_bytes, npb * cpp * bursts) <= stride)
+ break;
+ }
+ *num_bursts = bursts;
+}
+
+static void ipu_plane_atomic_update(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+ struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+ plane);
+ struct ipu_plane *ipu_plane = to_ipu_plane(plane);
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct ipu_plane_state *ipu_state = to_ipu_plane_state(new_state);
+ struct drm_crtc_state *crtc_state = new_state->crtc->state;
+ struct drm_framebuffer *fb = new_state->fb;
+ struct drm_rect *dst = &new_state->dst;
+ unsigned long eba, ubo, vbo;
+ unsigned long alpha_eba = 0;
+ enum ipu_color_space ics;
+ unsigned int axi_id = 0;
+ const struct drm_format_info *info;
+ u8 burstsize, num_bursts;
+ u32 width, height;
+ int active;
+
+ if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG)
+ ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1);
+
+ switch (ipu_plane->dp_flow) {
+ case IPU_DP_FLOW_SYNC_BG:
+ if (new_state->normalized_zpos == 1) {
+ ipu_dp_set_global_alpha(ipu_plane->dp,
+ !fb->format->has_alpha, 0xff,
+ true);
+ } else {
+ ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
+ }
+ break;
+ case IPU_DP_FLOW_SYNC_FG:
+ if (new_state->normalized_zpos == 1) {
+ ipu_dp_set_global_alpha(ipu_plane->dp,
+ !fb->format->has_alpha, 0xff,
+ false);
+ }
+ break;
+ }
+
+ if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_BG)
+ width = ipu_src_rect_width(new_state);
+ else
+ width = drm_rect_width(&new_state->src) >> 16;
+
+ eba = drm_plane_state_to_eba(new_state, 0);
+
+ /*
+ * Configure PRG channel and attached PRE, this changes the EBA to an
+ * internal SRAM location.
+ */
+ if (ipu_state->use_pre) {
+ axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
+ ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id, width,
+ drm_rect_height(&new_state->src) >> 16,
+ fb->pitches[0], fb->format->format,
+ fb->modifier, &eba);
+ }
+
+ if (!old_state->fb ||
+ old_state->fb->format->format != fb->format->format ||
+ old_state->color_encoding != new_state->color_encoding ||
+ old_state->color_range != new_state->color_range) {
+ ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
+ switch (ipu_plane->dp_flow) {
+ case IPU_DP_FLOW_SYNC_BG:
+ ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
+ new_state->color_range, ics,
+ IPUV3_COLORSPACE_RGB);
+ break;
+ case IPU_DP_FLOW_SYNC_FG:
+ ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
+ new_state->color_range, ics,
+ IPUV3_COLORSPACE_UNKNOWN);
+ break;
+ }
+ }
+
+ if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {
+ /* nothing to do if PRE is used */
+ if (ipu_state->use_pre)
+ return;
+ active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
+ ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
+ ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
+ if (ipu_plane_separate_alpha(ipu_plane)) {
+ active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
+ ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
+ alpha_eba);
+ ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active);
+ }
+ return;
+ }
+
+ ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
+ switch (ipu_plane->dp_flow) {
+ case IPU_DP_FLOW_SYNC_BG:
+ ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
+ IPUV3_COLORSPACE_RGB);
+ break;
+ case IPU_DP_FLOW_SYNC_FG:
+ ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
+ IPUV3_COLORSPACE_UNKNOWN);
+ break;
+ }
+
+ ipu_dmfc_config_wait4eot(ipu_plane->dmfc, width);
+
+ height = drm_rect_height(&new_state->src) >> 16;
+ info = drm_format_info(fb->format->format);
+ ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
+ &burstsize, &num_bursts);
+
+ ipu_cpmem_zero(ipu_plane->ipu_ch);
+ ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
+ ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
+ ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
+ ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
+ ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
+ ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
+ ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
+ ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
+
+ switch (fb->format->format) {
+ case DRM_FORMAT_YUV420:
+ case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YUV444:
+ case DRM_FORMAT_YVU444:
+ ubo = drm_plane_state_to_ubo(new_state);
+ vbo = drm_plane_state_to_vbo(new_state);
+ if (fb->format->format == DRM_FORMAT_YVU420 ||
+ fb->format->format == DRM_FORMAT_YVU422 ||
+ fb->format->format == DRM_FORMAT_YVU444)
+ swap(ubo, vbo);
+
+ ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
+ fb->pitches[1], ubo, vbo);
+
+ dev_dbg(ipu_plane->base.dev->dev,
+ "phy = %lu %lu %lu, x = %d, y = %d", eba, ubo, vbo,
+ new_state->src.x1 >> 16, new_state->src.y1 >> 16);
+ break;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV16:
+ ubo = drm_plane_state_to_ubo(new_state);
+
+ ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
+ fb->pitches[1], ubo, ubo);
+
+ dev_dbg(ipu_plane->base.dev->dev,
+ "phy = %lu %lu, x = %d, y = %d", eba, ubo,
+ new_state->src.x1 >> 16, new_state->src.y1 >> 16);
+ break;
+ case DRM_FORMAT_RGB565_A8:
+ case DRM_FORMAT_BGR565_A8:
+ case DRM_FORMAT_RGB888_A8:
+ case DRM_FORMAT_BGR888_A8:
+ case DRM_FORMAT_RGBX8888_A8:
+ case DRM_FORMAT_BGRX8888_A8:
+ alpha_eba = drm_plane_state_to_eba(new_state, 1);
+ num_bursts = 0;
+
+ dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d",
+ eba, alpha_eba, new_state->src.x1 >> 16,
+ new_state->src.y1 >> 16);
+
+ ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
+
+ ipu_cpmem_zero(ipu_plane->alpha_ch);
+ ipu_cpmem_set_resolution(ipu_plane->alpha_ch, width,
+ drm_rect_height(&new_state->src) >> 16);
+ ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
+ ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
+ ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);
+ ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]);
+ ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16);
+ ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba);
+ ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba);
+ break;
+ default:
+ dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d",
+ eba, new_state->src.x1 >> 16, new_state->src.y1 >> 16);
+ break;
+ }
+ ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
+ ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
+ ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
+ ipu_plane_enable(ipu_plane);
+}
+
+static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
+ .atomic_check = ipu_plane_atomic_check,
+ .atomic_disable = ipu_plane_atomic_disable,
+ .atomic_update = ipu_plane_atomic_update,
+};
+
+bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
+{
+ struct ipu_plane *ipu_plane = to_ipu_plane(plane);
+ struct drm_plane_state *state = plane->state;
+ struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
+
+ /* disabled crtcs must not block the update */
+ if (!state->crtc)
+ return false;
+
+ if (ipu_state->use_pre)
+ return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
+
+ /*
+ * Pretend no update is pending in the non-PRE/PRG case. For this to
+ * happen, an atomic update would have to be deferred until after the
+ * start of the next frame and simultaneously interrupt latency would
+ * have to be high enough to let the atomic update finish and issue an
+ * event before the previous end of frame interrupt handler can be
+ * executed.
+ */
+ return false;
+}
+int ipu_planes_assign_pre(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *old_crtc_state, *crtc_state;
+ struct drm_plane_state *plane_state;
+ struct ipu_plane_state *ipu_state;
+ struct ipu_plane *ipu_plane;
+ struct drm_plane *plane;
+ struct drm_crtc *crtc;
+ int available_pres = ipu_prg_max_active_channels();
+ int ret, i;
+
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
+ ret = drm_atomic_add_affected_planes(state, crtc);
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * We are going over the planes in 2 passes: first we assign PREs to
+ * planes with a tiling modifier, which need the PREs to resolve into
+ * linear. Any failure to assign a PRE there is fatal. In the second
+ * pass we try to assign PREs to linear FBs, to improve memory access
+ * patterns for them. Failure at this point is non-fatal, as we can
+ * scan out linear FBs without a PRE.
+ */
+ for_each_new_plane_in_state(state, plane, plane_state, i) {
+ ipu_state = to_ipu_plane_state(plane_state);
+ ipu_plane = to_ipu_plane(plane);
+
+ if (!plane_state->fb) {
+ ipu_state->use_pre = false;
+ continue;
+ }
+
+ if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
+ plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
+ continue;
+
+ if (!ipu_prg_present(ipu_plane->ipu) || !available_pres)
+ return -EINVAL;
+
+ if (!ipu_prg_format_supported(ipu_plane->ipu,
+ plane_state->fb->format->format,
+ plane_state->fb->modifier))
+ return -EINVAL;
+
+ ipu_state->use_pre = true;
+ available_pres--;
+ }
+
+ for_each_new_plane_in_state(state, plane, plane_state, i) {
+ ipu_state = to_ipu_plane_state(plane_state);
+ ipu_plane = to_ipu_plane(plane);
+
+ if (!plane_state->fb) {
+ ipu_state->use_pre = false;
+ continue;
+ }
+
+ if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
+ plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
+ continue;
+
+ /* make sure that modifier is initialized */
+ plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
+
+ if (ipu_prg_present(ipu_plane->ipu) && available_pres &&
+ ipu_prg_format_supported(ipu_plane->ipu,
+ plane_state->fb->format->format,
+ plane_state->fb->modifier)) {
+ ipu_state->use_pre = true;
+ available_pres--;
+ } else {
+ ipu_state->use_pre = false;
+ }
+ }
+
+ return 0;
+}
+
+struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
+ int dma, int dp, unsigned int possible_crtcs,
+ enum drm_plane_type type)
+{
+ struct ipu_plane *ipu_plane;
+ const uint64_t *modifiers = ipu_format_modifiers;
+ unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
+ unsigned int format_count;
+ const uint32_t *formats;
+ int ret;
+
+ DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
+ dma, dp, possible_crtcs);
+
+ if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG) {
+ formats = ipu_plane_all_formats;
+ format_count = ARRAY_SIZE(ipu_plane_all_formats);
+ } else {
+ formats = ipu_plane_rgb_formats;
+ format_count = ARRAY_SIZE(ipu_plane_rgb_formats);
+ }
+
+ if (ipu_prg_present(ipu))
+ modifiers = pre_format_modifiers;
+
+ ipu_plane = drmm_universal_plane_alloc(dev, struct ipu_plane, base,
+ possible_crtcs, &ipu_plane_funcs,
+ formats, format_count, modifiers,
+ type, NULL);
+ if (IS_ERR(ipu_plane)) {
+ DRM_ERROR("failed to allocate and initialize %s plane\n",
+ zpos ? "overlay" : "primary");
+ return ipu_plane;
+ }
+
+ ipu_plane->ipu = ipu;
+ ipu_plane->dma = dma;
+ ipu_plane->dp_flow = dp;
+
+ drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs);
+
+ if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG)
+ ret = drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0,
+ 1);
+ else
+ ret = drm_plane_create_zpos_immutable_property(&ipu_plane->base,
+ 0);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = drm_plane_create_color_properties(&ipu_plane->base,
+ BIT(DRM_COLOR_YCBCR_BT601) |
+ BIT(DRM_COLOR_YCBCR_BT709),
+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
+ DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_LIMITED_RANGE);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = ipu_plane_get_resources(dev, ipu_plane);
+ if (ret) {
+ DRM_ERROR("failed to get %s plane resources: %pe\n",
+ zpos ? "overlay" : "primary", &ret);
+ return ERR_PTR(ret);
+ }
+
+ return ipu_plane;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __IPUV3_PLANE_H__
+#define __IPUV3_PLANE_H__
+
+#include <drm/drm_crtc.h> /* drm_plane */
+
+struct drm_plane;
+struct drm_device;
+struct ipu_soc;
+struct drm_crtc;
+struct drm_framebuffer;
+
+struct ipuv3_channel;
+struct dmfc_channel;
+struct ipu_dp;
+
+struct ipu_plane {
+ struct drm_plane base;
+
+ struct ipu_soc *ipu;
+ struct ipuv3_channel *ipu_ch;
+ struct ipuv3_channel *alpha_ch;
+ struct dmfc_channel *dmfc;
+ struct ipu_dp *dp;
+
+ int dma;
+ int dp_flow;
+
+ bool disabling;
+};
+
+struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
+ int dma, int dp, unsigned int possible_crtcs,
+ enum drm_plane_type type);
+
+/* Init IDMAC, DMFC, DP */
+int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_framebuffer *fb, int crtc_x, int crtc_y,
+ unsigned int crtc_w, unsigned int crtc_h,
+ uint32_t src_x, uint32_t src_y, uint32_t src_w,
+ uint32_t src_h, bool interlaced);
+
+int ipu_plane_irq(struct ipu_plane *plane);
+
+void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel);
+void ipu_plane_disable_deferred(struct drm_plane *plane);
+bool ipu_plane_atomic_update_pending(struct drm_plane *plane);
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX drm driver - parallel display implementation
+ *
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix
+ */
+
+#include <linux/component.h>
+#include <linux/media-bus-format.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/videodev2.h>
+
+#include <video/of_display_timing.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include "imx-drm.h"
+
+struct imx_parallel_display_encoder {
+ struct drm_connector connector;
+ struct drm_encoder encoder;
+ struct drm_bridge bridge;
+ struct imx_parallel_display *pd;
+};
+
+struct imx_parallel_display {
+ struct device *dev;
+ void *edid;
+ u32 bus_format;
+ u32 bus_flags;
+ struct drm_display_mode mode;
+ struct drm_panel *panel;
+ struct drm_bridge *next_bridge;
+};
+
+static inline struct imx_parallel_display *con_to_imxpd(struct drm_connector *c)
+{
+ return container_of(c, struct imx_parallel_display_encoder, connector)->pd;
+}
+
+static inline struct imx_parallel_display *bridge_to_imxpd(struct drm_bridge *b)
+{
+ return container_of(b, struct imx_parallel_display_encoder, bridge)->pd;
+}
+
+static int imx_pd_connector_get_modes(struct drm_connector *connector)
+{
+ struct imx_parallel_display *imxpd = con_to_imxpd(connector);
+ struct device_node *np = imxpd->dev->of_node;
+ int num_modes;
+
+ num_modes = drm_panel_get_modes(imxpd->panel, connector);
+ if (num_modes > 0)
+ return num_modes;
+
+ if (imxpd->edid) {
+ drm_connector_update_edid_property(connector, imxpd->edid);
+ num_modes = drm_add_edid_modes(connector, imxpd->edid);
+ }
+
+ if (np) {
+ struct drm_display_mode *mode = drm_mode_create(connector->dev);
+ int ret;
+
+ if (!mode)
+ return -EINVAL;
+
+ ret = of_get_drm_display_mode(np, &imxpd->mode,
+ &imxpd->bus_flags,
+ OF_USE_NATIVE_MODE);
+ if (ret) {
+ drm_mode_destroy(connector->dev, mode);
+ return ret;
+ }
+
+ drm_mode_copy(mode, &imxpd->mode);
+ mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+ drm_mode_probed_add(connector, mode);
+ num_modes++;
+ }
+
+ return num_modes;
+}
+
+static void imx_pd_bridge_enable(struct drm_bridge *bridge)
+{
+ struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
+
+ drm_panel_prepare(imxpd->panel);
+ drm_panel_enable(imxpd->panel);
+}
+
+static void imx_pd_bridge_disable(struct drm_bridge *bridge)
+{
+ struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
+
+ drm_panel_disable(imxpd->panel);
+ drm_panel_unprepare(imxpd->panel);
+}
+
+static const u32 imx_pd_bus_fmts[] = {
+ MEDIA_BUS_FMT_RGB888_1X24,
+ MEDIA_BUS_FMT_BGR888_1X24,
+ MEDIA_BUS_FMT_GBR888_1X24,
+ MEDIA_BUS_FMT_RGB666_1X18,
+ MEDIA_BUS_FMT_RGB666_1X24_CPADHI,
+ MEDIA_BUS_FMT_RGB565_1X16,
+};
+
+static u32 *
+imx_pd_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ struct drm_display_info *di = &conn_state->connector->display_info;
+ struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
+ u32 *output_fmts;
+
+ if (!imxpd->bus_format && !di->num_bus_formats) {
+ *num_output_fmts = ARRAY_SIZE(imx_pd_bus_fmts);
+ return kmemdup(imx_pd_bus_fmts, sizeof(imx_pd_bus_fmts),
+ GFP_KERNEL);
+ }
+
+ *num_output_fmts = 1;
+ output_fmts = kmalloc(sizeof(*output_fmts), GFP_KERNEL);
+ if (!output_fmts)
+ return NULL;
+
+ if (!imxpd->bus_format && di->num_bus_formats)
+ output_fmts[0] = di->bus_formats[0];
+ else
+ output_fmts[0] = imxpd->bus_format;
+
+ return output_fmts;
+}
+
+static bool imx_pd_format_supported(u32 output_fmt)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx_pd_bus_fmts); i++) {
+ if (imx_pd_bus_fmts[i] == output_fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx_pd_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
+ u32 *input_fmts;
+
+ /*
+ * If the next bridge does not support bus format negotiation, let's
+ * use the static bus format definition (imxpd->bus_format) if it's
+ * specified, RGB888 when it's not.
+ */
+ if (output_fmt == MEDIA_BUS_FMT_FIXED)
+ output_fmt = imxpd->bus_format ? : MEDIA_BUS_FMT_RGB888_1X24;
+
+ /* Now make sure the requested output format is supported. */
+ if ((imxpd->bus_format && imxpd->bus_format != output_fmt) ||
+ !imx_pd_format_supported(output_fmt)) {
+ *num_input_fmts = 0;
+ return NULL;
+ }
+
+ *num_input_fmts = 1;
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ input_fmts[0] = output_fmt;
+ return input_fmts;
+}
+
+static int imx_pd_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
+ struct drm_display_info *di = &conn_state->connector->display_info;
+ struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
+ struct drm_bridge_state *next_bridge_state = NULL;
+ struct drm_bridge *next_bridge;
+ u32 bus_flags, bus_fmt;
+
+ next_bridge = drm_bridge_get_next_bridge(bridge);
+ if (next_bridge)
+ next_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,
+ next_bridge);
+
+ if (next_bridge_state)
+ bus_flags = next_bridge_state->input_bus_cfg.flags;
+ else if (di->num_bus_formats)
+ bus_flags = di->bus_flags;
+ else
+ bus_flags = imxpd->bus_flags;
+
+ bus_fmt = bridge_state->input_bus_cfg.format;
+ if (!imx_pd_format_supported(bus_fmt))
+ return -EINVAL;
+
+ bridge_state->output_bus_cfg.flags = bus_flags;
+ bridge_state->input_bus_cfg.flags = bus_flags;
+ imx_crtc_state->bus_flags = bus_flags;
+ imx_crtc_state->bus_format = bridge_state->input_bus_cfg.format;
+ imx_crtc_state->di_hsync_pin = 2;
+ imx_crtc_state->di_vsync_pin = 3;
+
+ return 0;
+}
+
+static const struct drm_connector_funcs imx_pd_connector_funcs = {
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = imx_drm_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_connector_helper_funcs imx_pd_connector_helper_funcs = {
+ .get_modes = imx_pd_connector_get_modes,
+};
+
+static const struct drm_bridge_funcs imx_pd_bridge_funcs = {
+ .enable = imx_pd_bridge_enable,
+ .disable = imx_pd_bridge_disable,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_check = imx_pd_bridge_atomic_check,
+ .atomic_get_input_bus_fmts = imx_pd_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts = imx_pd_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx_pd_bind(struct device *dev, struct device *master, void *data)
+{
+ struct drm_device *drm = data;
+ struct imx_parallel_display *imxpd = dev_get_drvdata(dev);
+ struct imx_parallel_display_encoder *imxpd_encoder;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+ struct drm_bridge *bridge;
+ int ret;
+
+ imxpd_encoder = drmm_simple_encoder_alloc(drm, struct imx_parallel_display_encoder,
+ encoder, DRM_MODE_ENCODER_NONE);
+ if (IS_ERR(imxpd_encoder))
+ return PTR_ERR(imxpd_encoder);
+
+ imxpd_encoder->pd = imxpd;
+ connector = &imxpd_encoder->connector;
+ encoder = &imxpd_encoder->encoder;
+ bridge = &imxpd_encoder->bridge;
+
+ ret = imx_drm_encoder_parse_of(drm, encoder, imxpd->dev->of_node);
+ if (ret)
+ return ret;
+
+ /* set the connector's dpms to OFF so that
+ * drm_helper_connector_dpms() won't return
+ * immediately since the current state is ON
+ * at this point.
+ */
+ connector->dpms = DRM_MODE_DPMS_OFF;
+
+ bridge->funcs = &imx_pd_bridge_funcs;
+ drm_bridge_attach(encoder, bridge, NULL, 0);
+
+ if (imxpd->next_bridge) {
+ ret = drm_bridge_attach(encoder, imxpd->next_bridge, bridge, 0);
+ if (ret < 0)
+ return ret;
+ } else {
+ drm_connector_helper_add(connector,
+ &imx_pd_connector_helper_funcs);
+ drm_connector_init(drm, connector, &imx_pd_connector_funcs,
+ DRM_MODE_CONNECTOR_DPI);
+
+ drm_connector_attach_encoder(connector, encoder);
+ }
+
+ return 0;
+}
+
+static const struct component_ops imx_pd_ops = {
+ .bind = imx_pd_bind,
+};
+
+static int imx_pd_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const u8 *edidp;
+ struct imx_parallel_display *imxpd;
+ int edid_len;
+ int ret;
+ u32 bus_format = 0;
+ const char *fmt;
+
+ imxpd = devm_kzalloc(dev, sizeof(*imxpd), GFP_KERNEL);
+ if (!imxpd)
+ return -ENOMEM;
+
+ /* port@1 is the output port */
+ ret = drm_of_find_panel_or_bridge(np, 1, 0, &imxpd->panel,
+ &imxpd->next_bridge);
+ if (ret && ret != -ENODEV)
+ return ret;
+
+ edidp = of_get_property(np, "edid", &edid_len);
+ if (edidp)
+ imxpd->edid = devm_kmemdup(dev, edidp, edid_len, GFP_KERNEL);
+
+ ret = of_property_read_string(np, "interface-pix-fmt", &fmt);
+ if (!ret) {
+ if (!strcmp(fmt, "rgb24"))
+ bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ else if (!strcmp(fmt, "rgb565"))
+ bus_format = MEDIA_BUS_FMT_RGB565_1X16;
+ else if (!strcmp(fmt, "bgr666"))
+ bus_format = MEDIA_BUS_FMT_RGB666_1X18;
+ else if (!strcmp(fmt, "lvds666"))
+ bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
+ }
+ imxpd->bus_format = bus_format;
+
+ imxpd->dev = dev;
+
+ platform_set_drvdata(pdev, imxpd);
+
+ return component_add(dev, &imx_pd_ops);
+}
+
+static int imx_pd_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &imx_pd_ops);
+
+ return 0;
+}
+
+static const struct of_device_id imx_pd_dt_ids[] = {
+ { .compatible = "fsl,imx-parallel-display", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_pd_dt_ids);
+
+static struct platform_driver imx_pd_driver = {
+ .probe = imx_pd_probe,
+ .remove = imx_pd_remove,
+ .driver = {
+ .of_match_table = imx_pd_dt_ids,
+ .name = "imx-parallel-display",
+ },
+};
+
+module_platform_driver(imx_pd_driver);
+
+MODULE_DESCRIPTION("i.MX parallel display driver");
+MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:imx-parallel-display");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * i.MX drm driver - parallel display implementation
- *
- * Copyright (C) 2012 Sascha Hauer, Pengutronix
- */
-
-#include <linux/component.h>
-#include <linux/media-bus-format.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/videodev2.h>
-
-#include <video/of_display_timing.h>
-
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_bridge.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_managed.h>
-#include <drm/drm_of.h>
-#include <drm/drm_panel.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_simple_kms_helper.h>
-
-#include "imx-drm.h"
-
-struct imx_parallel_display_encoder {
- struct drm_connector connector;
- struct drm_encoder encoder;
- struct drm_bridge bridge;
- struct imx_parallel_display *pd;
-};
-
-struct imx_parallel_display {
- struct device *dev;
- void *edid;
- u32 bus_format;
- u32 bus_flags;
- struct drm_display_mode mode;
- struct drm_panel *panel;
- struct drm_bridge *next_bridge;
-};
-
-static inline struct imx_parallel_display *con_to_imxpd(struct drm_connector *c)
-{
- return container_of(c, struct imx_parallel_display_encoder, connector)->pd;
-}
-
-static inline struct imx_parallel_display *bridge_to_imxpd(struct drm_bridge *b)
-{
- return container_of(b, struct imx_parallel_display_encoder, bridge)->pd;
-}
-
-static int imx_pd_connector_get_modes(struct drm_connector *connector)
-{
- struct imx_parallel_display *imxpd = con_to_imxpd(connector);
- struct device_node *np = imxpd->dev->of_node;
- int num_modes;
-
- num_modes = drm_panel_get_modes(imxpd->panel, connector);
- if (num_modes > 0)
- return num_modes;
-
- if (imxpd->edid) {
- drm_connector_update_edid_property(connector, imxpd->edid);
- num_modes = drm_add_edid_modes(connector, imxpd->edid);
- }
-
- if (np) {
- struct drm_display_mode *mode = drm_mode_create(connector->dev);
- int ret;
-
- if (!mode)
- return -EINVAL;
-
- ret = of_get_drm_display_mode(np, &imxpd->mode,
- &imxpd->bus_flags,
- OF_USE_NATIVE_MODE);
- if (ret) {
- drm_mode_destroy(connector->dev, mode);
- return ret;
- }
-
- drm_mode_copy(mode, &imxpd->mode);
- mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
- drm_mode_probed_add(connector, mode);
- num_modes++;
- }
-
- return num_modes;
-}
-
-static void imx_pd_bridge_enable(struct drm_bridge *bridge)
-{
- struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
-
- drm_panel_prepare(imxpd->panel);
- drm_panel_enable(imxpd->panel);
-}
-
-static void imx_pd_bridge_disable(struct drm_bridge *bridge)
-{
- struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
-
- drm_panel_disable(imxpd->panel);
- drm_panel_unprepare(imxpd->panel);
-}
-
-static const u32 imx_pd_bus_fmts[] = {
- MEDIA_BUS_FMT_RGB888_1X24,
- MEDIA_BUS_FMT_BGR888_1X24,
- MEDIA_BUS_FMT_GBR888_1X24,
- MEDIA_BUS_FMT_RGB666_1X18,
- MEDIA_BUS_FMT_RGB666_1X24_CPADHI,
- MEDIA_BUS_FMT_RGB565_1X16,
-};
-
-static u32 *
-imx_pd_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
- struct drm_bridge_state *bridge_state,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state,
- unsigned int *num_output_fmts)
-{
- struct drm_display_info *di = &conn_state->connector->display_info;
- struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
- u32 *output_fmts;
-
- if (!imxpd->bus_format && !di->num_bus_formats) {
- *num_output_fmts = ARRAY_SIZE(imx_pd_bus_fmts);
- return kmemdup(imx_pd_bus_fmts, sizeof(imx_pd_bus_fmts),
- GFP_KERNEL);
- }
-
- *num_output_fmts = 1;
- output_fmts = kmalloc(sizeof(*output_fmts), GFP_KERNEL);
- if (!output_fmts)
- return NULL;
-
- if (!imxpd->bus_format && di->num_bus_formats)
- output_fmts[0] = di->bus_formats[0];
- else
- output_fmts[0] = imxpd->bus_format;
-
- return output_fmts;
-}
-
-static bool imx_pd_format_supported(u32 output_fmt)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(imx_pd_bus_fmts); i++) {
- if (imx_pd_bus_fmts[i] == output_fmt)
- return true;
- }
-
- return false;
-}
-
-static u32 *
-imx_pd_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
- struct drm_bridge_state *bridge_state,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state,
- u32 output_fmt,
- unsigned int *num_input_fmts)
-{
- struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
- u32 *input_fmts;
-
- /*
- * If the next bridge does not support bus format negotiation, let's
- * use the static bus format definition (imxpd->bus_format) if it's
- * specified, RGB888 when it's not.
- */
- if (output_fmt == MEDIA_BUS_FMT_FIXED)
- output_fmt = imxpd->bus_format ? : MEDIA_BUS_FMT_RGB888_1X24;
-
- /* Now make sure the requested output format is supported. */
- if ((imxpd->bus_format && imxpd->bus_format != output_fmt) ||
- !imx_pd_format_supported(output_fmt)) {
- *num_input_fmts = 0;
- return NULL;
- }
-
- *num_input_fmts = 1;
- input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
- if (!input_fmts)
- return NULL;
-
- input_fmts[0] = output_fmt;
- return input_fmts;
-}
-
-static int imx_pd_bridge_atomic_check(struct drm_bridge *bridge,
- struct drm_bridge_state *bridge_state,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
- struct drm_display_info *di = &conn_state->connector->display_info;
- struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge);
- struct drm_bridge_state *next_bridge_state = NULL;
- struct drm_bridge *next_bridge;
- u32 bus_flags, bus_fmt;
-
- next_bridge = drm_bridge_get_next_bridge(bridge);
- if (next_bridge)
- next_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,
- next_bridge);
-
- if (next_bridge_state)
- bus_flags = next_bridge_state->input_bus_cfg.flags;
- else if (di->num_bus_formats)
- bus_flags = di->bus_flags;
- else
- bus_flags = imxpd->bus_flags;
-
- bus_fmt = bridge_state->input_bus_cfg.format;
- if (!imx_pd_format_supported(bus_fmt))
- return -EINVAL;
-
- bridge_state->output_bus_cfg.flags = bus_flags;
- bridge_state->input_bus_cfg.flags = bus_flags;
- imx_crtc_state->bus_flags = bus_flags;
- imx_crtc_state->bus_format = bridge_state->input_bus_cfg.format;
- imx_crtc_state->di_hsync_pin = 2;
- imx_crtc_state->di_vsync_pin = 3;
-
- return 0;
-}
-
-static const struct drm_connector_funcs imx_pd_connector_funcs = {
- .fill_modes = drm_helper_probe_single_connector_modes,
- .destroy = imx_drm_connector_destroy,
- .reset = drm_atomic_helper_connector_reset,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static const struct drm_connector_helper_funcs imx_pd_connector_helper_funcs = {
- .get_modes = imx_pd_connector_get_modes,
-};
-
-static const struct drm_bridge_funcs imx_pd_bridge_funcs = {
- .enable = imx_pd_bridge_enable,
- .disable = imx_pd_bridge_disable,
- .atomic_reset = drm_atomic_helper_bridge_reset,
- .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
- .atomic_check = imx_pd_bridge_atomic_check,
- .atomic_get_input_bus_fmts = imx_pd_bridge_atomic_get_input_bus_fmts,
- .atomic_get_output_bus_fmts = imx_pd_bridge_atomic_get_output_bus_fmts,
-};
-
-static int imx_pd_bind(struct device *dev, struct device *master, void *data)
-{
- struct drm_device *drm = data;
- struct imx_parallel_display *imxpd = dev_get_drvdata(dev);
- struct imx_parallel_display_encoder *imxpd_encoder;
- struct drm_connector *connector;
- struct drm_encoder *encoder;
- struct drm_bridge *bridge;
- int ret;
-
- imxpd_encoder = drmm_simple_encoder_alloc(drm, struct imx_parallel_display_encoder,
- encoder, DRM_MODE_ENCODER_NONE);
- if (IS_ERR(imxpd_encoder))
- return PTR_ERR(imxpd_encoder);
-
- imxpd_encoder->pd = imxpd;
- connector = &imxpd_encoder->connector;
- encoder = &imxpd_encoder->encoder;
- bridge = &imxpd_encoder->bridge;
-
- ret = imx_drm_encoder_parse_of(drm, encoder, imxpd->dev->of_node);
- if (ret)
- return ret;
-
- /* set the connector's dpms to OFF so that
- * drm_helper_connector_dpms() won't return
- * immediately since the current state is ON
- * at this point.
- */
- connector->dpms = DRM_MODE_DPMS_OFF;
-
- bridge->funcs = &imx_pd_bridge_funcs;
- drm_bridge_attach(encoder, bridge, NULL, 0);
-
- if (imxpd->next_bridge) {
- ret = drm_bridge_attach(encoder, imxpd->next_bridge, bridge, 0);
- if (ret < 0)
- return ret;
- } else {
- drm_connector_helper_add(connector,
- &imx_pd_connector_helper_funcs);
- drm_connector_init(drm, connector, &imx_pd_connector_funcs,
- DRM_MODE_CONNECTOR_DPI);
-
- drm_connector_attach_encoder(connector, encoder);
- }
-
- return 0;
-}
-
-static const struct component_ops imx_pd_ops = {
- .bind = imx_pd_bind,
-};
-
-static int imx_pd_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- const u8 *edidp;
- struct imx_parallel_display *imxpd;
- int edid_len;
- int ret;
- u32 bus_format = 0;
- const char *fmt;
-
- imxpd = devm_kzalloc(dev, sizeof(*imxpd), GFP_KERNEL);
- if (!imxpd)
- return -ENOMEM;
-
- /* port@1 is the output port */
- ret = drm_of_find_panel_or_bridge(np, 1, 0, &imxpd->panel,
- &imxpd->next_bridge);
- if (ret && ret != -ENODEV)
- return ret;
-
- edidp = of_get_property(np, "edid", &edid_len);
- if (edidp)
- imxpd->edid = devm_kmemdup(dev, edidp, edid_len, GFP_KERNEL);
-
- ret = of_property_read_string(np, "interface-pix-fmt", &fmt);
- if (!ret) {
- if (!strcmp(fmt, "rgb24"))
- bus_format = MEDIA_BUS_FMT_RGB888_1X24;
- else if (!strcmp(fmt, "rgb565"))
- bus_format = MEDIA_BUS_FMT_RGB565_1X16;
- else if (!strcmp(fmt, "bgr666"))
- bus_format = MEDIA_BUS_FMT_RGB666_1X18;
- else if (!strcmp(fmt, "lvds666"))
- bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
- }
- imxpd->bus_format = bus_format;
-
- imxpd->dev = dev;
-
- platform_set_drvdata(pdev, imxpd);
-
- return component_add(dev, &imx_pd_ops);
-}
-
-static int imx_pd_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &imx_pd_ops);
-
- return 0;
-}
-
-static const struct of_device_id imx_pd_dt_ids[] = {
- { .compatible = "fsl,imx-parallel-display", },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, imx_pd_dt_ids);
-
-static struct platform_driver imx_pd_driver = {
- .probe = imx_pd_probe,
- .remove = imx_pd_remove,
- .driver = {
- .of_match_table = imx_pd_dt_ids,
- .name = "imx-parallel-display",
- },
-};
-
-module_platform_driver(imx_pd_driver);
-
-MODULE_DESCRIPTION("i.MX parallel display driver");
-MODULE_AUTHOR("Sascha Hauer, Pengutronix");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:imx-parallel-display");
projects / linux.git / commitdiff