coresight: etm3x: Cleanup ETMTECR1 register accesses

This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. These fields already have macros
to define them so use them instead of magic numbers.

Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-11-james.clark@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index 7d413ba8b823c9a22d38331afb9c803d8cc214bf..d0ab9933472bcfa5974e0546d37e1d90bee9f85b 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -204,7 +204,7 @@ void etm_set_default(struct etm_config *config)
         *  set all bits in register 0x007, the ETMTECR2, to 0
         *  set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
         */
-       config->enable_ctrl1 = BIT(24);
+       config->enable_ctrl1 = ETMTECR1_INC_EXC;
        config->enable_ctrl2 = 0x0;
        config->enable_event = ETM_HARD_WIRE_RES_A;
 

diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
index e8c7649f123e735dcd17219535a148c52922bc60..68fcbf4ce7a8e3fc25719619abf150fa8ecb6542 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
@@ -474,7 +474,7 @@ static ssize_t addr_start_store(struct device *dev,
        config->addr_val[idx] = val;
        config->addr_type[idx] = ETM_ADDR_TYPE_START;
        config->startstop_ctrl |= (1 << idx);
-       config->enable_ctrl1 |= BIT(25);
+       config->enable_ctrl1 |= ETMTECR1_START_STOP;
        spin_unlock(&drvdata->spinlock);
 
        return size;