}
static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
{
- struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
+ struct ath5k_hw *ah = hw_priv;
return ath5k_hw_reg_read(ah, reg_offset);
}
static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
{
- struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
+ struct ath5k_hw *ah = hw_priv;
ath5k_hw_reg_write(ah, val, reg_offset);
}
/* return bus cachesize in 4B word units */
static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
{
- struct ath5k_hw *ah = (struct ath5k_hw *) common->priv;
+ struct ath5k_hw *ah = common->priv;
u8 u8tmp;
pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
static bool
ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
{
- struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
+ struct ath5k_hw *ah = common->ah;
u32 status, timeout;
/*