mmc: sdhci-pci-o2micro: Improve card input timing at SDR104/HS200 mode

Card input timing is margin, need to adjust the hold timing of card input.

Signed-off-by: Fred Ai <fred.ai@bayhubtech.com>
Link: https://lore.kernel.org/r/20211221040940.484-1-fred.ai@bayhubtech.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
index f045c1ee4667a9df8018d276efd2f5a7c7b7e96d..56e9f93999c4ab5af85895cf13bbc9425694a009 100644 (file)
--- a/drivers/mmc/host/sdhci-pci-o2micro.c
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -12,6 +12,7 @@
 #include <linux/mmc/mmc.h>
 #include <linux/delay.h>
 #include <linux/iopoll.h>
+#include <linux/bitfield.h>
 
 #include "sdhci.h"
 #include "sdhci-pci.h"
@@ -43,12 +44,16 @@
 #define O2_SD_CAP_REG0         0x334
 #define O2_SD_UHS1_CAP_SETTING 0x33C
 #define O2_SD_DELAY_CTRL       0x350
+#define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354
 #define O2_SD_UHS2_L1_CTRL     0x35C
 #define O2_SD_FUNC_REG3                0x3E0
 #define O2_SD_FUNC_REG4                0x3E4
 #define O2_SD_LED_ENABLE       BIT(6)
 #define O2_SD_FREG0_LEDOFF     BIT(13)
+#define O2_SD_SEL_DLL          BIT(16)
 #define O2_SD_FREG4_ENABLE_CLK_SET     BIT(22)
+#define O2_SD_PHASE_MASK       GENMASK(23, 20)
+#define O2_SD_FIX_PHASE                FIELD_PREP(O2_SD_PHASE_MASK, 0x9)
 
 #define O2_SD_VENDOR_SETTING   0x110
 #define O2_SD_VENDOR_SETTING2  0x1C8
@@ -301,9 +306,13 @@ static int sdhci_o2_dll_recovery(struct sdhci_host *host)
 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
 {
        struct sdhci_host *host = mmc_priv(mmc);
+       struct sdhci_pci_slot *slot = sdhci_priv(host);
+       struct sdhci_pci_chip *chip = slot->chip;
        int current_bus_width = 0;
        u32 scratch32 = 0;
        u16 scratch = 0;
+       u8  scratch_8 = 0;
+       u32 reg_val;
 
        /*
         * This handler only implements the eMMC tuning that is specific to
@@ -322,6 +331,32 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
        scratch |= O2_SD_PWR_FORCE_L0;
        sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
 
+       /* Stop clk */
+       reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+       reg_val &= ~SDHCI_CLOCK_CARD_EN;
+       sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
+
+       /* UnLock WP */
+       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
+       scratch_8 &= 0x7f;
+       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
+
+       /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
+       pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
+       reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
+       reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
+       pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
+
+       /* Lock WP */
+       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
+       scratch_8 |= 0x80;
+       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
+
+       /* Start clk */
+       reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+       reg_val |= SDHCI_CLOCK_CARD_EN;
+       sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
+
        /* wait DLL lock, timeout value 5ms */
        if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
                scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
@@ -533,22 +568,26 @@ static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
        if (clock == 0)
                return;
 
-       if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
-               pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
-
-               scratch &= 0x7f;
-               pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+       /* UnLock WP */
+       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
+       scratch &= 0x7f;
+       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 
+       if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
                pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
 
                if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
                        o2_pci_set_baseclk(chip, 0x2c280000);
+       }
 
-               pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
+       pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);
+       scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
+       pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);
 
-               scratch |= 0x80;
-               pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
-       }
+       /* Lock WP */
+       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
+       scratch |= 0x80;
+       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 
        clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
        sdhci_o2_enable_clk(host, clk);