staging: iio: resolver: ad2s1210: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.  As the tx[] an rx[] buffers are only used
in the same SPI exchanges, we should be safe with them on the same cacheline.
Hence only mark the first one __aligned(IIO_DMA_MINALIGN).

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-5-jic23@kernel.org

diff --git a/drivers/staging/iio/resolver/ad2s1210.c b/drivers/staging/iio/resolver/ad2s1210.c
index c0b2716d05112ade9fb66ede9467c1ddf0f9892e..e4cf42438487d2f0e622b6f9a938fe31eaa9f92b 100644 (file)
--- a/drivers/staging/iio/resolver/ad2s1210.c
+++ b/drivers/staging/iio/resolver/ad2s1210.c
@@ -94,8 +94,8 @@ struct ad2s1210_state {
        bool hysteresis;
        u8 resolution;
        enum ad2s1210_mode mode;
-       u8 rx[2] ____cacheline_aligned;
-       u8 tx[2] ____cacheline_aligned;
+       u8 rx[2] __aligned(IIO_DMA_MINALIGN);
+       u8 tx[2];
 };
 
 static const int ad2s1210_mode_vals[4][2] = {