drm/xe/uc: Use u64 for offsets for which we use upper_32_bits()

The GGTT is currently a 32 bit address space, but the HW and GuC
support 48b addresses in GGTT-related operations, both to keep the
interface/HW paths common between PPGTT and GGTT and to allow for
future increase of the GGTT size.
This leaves us having to program a 64b field with a 32b offset, which
currently we're in some cases doing this by using an upper_32_bits()
call on a 32b variable, which doesn't make any sense. To do this cleanly
we have 2 options:

1 - Set the upper 32 bits directly to zero.
2 - Use 64b variables for the offset and keep programming the whole thing,
    so we're ready if we ever have bigger offsets.

This patch goes with option #2 and switches the related variables to u64.

v2: don't change the log ctl flag variable (John)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240319195101.2784480-1-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/xe/xe_guc_hwconfig.c b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
index 1173453c403948e805a36fb041de659651aa5bd5..f035ad59f68e111f5625d4351d080efc11e0b06b 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_hwconfig.c
+++ b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
@@ -14,7 +14,7 @@
 #include "xe_guc.h"
 #include "xe_map.h"
 
-static int send_get_hwconfig(struct xe_guc *guc, u32 ggtt_addr, u32 size)
+static int send_get_hwconfig(struct xe_guc *guc, u64 ggtt_addr, u32 size)
 {
        u32 action[] = {
                XE_GUC_ACTION_GET_HWCONFIG,

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index a71be57f0fc2332eece7d65d038004d4e56b88af..ce46ce22fa5f101fb4f3f3a52e3591110631121e 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -533,7 +533,7 @@ static void register_engine(struct xe_exec_queue *q)
        info.flags = CONTEXT_REGISTRATION_FLAG_KMD;
 
        if (xe_exec_queue_is_parallel(q)) {
-               u32 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);
+               u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);
                struct iosys_map map = xe_lrc_parallel_map(lrc);
 
                info.wq_desc_lo = lower_32_bits(ggtt_addr +

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 400651485b8598ef087cebe8ef3dc0663ed11676..3554f66872b9de6dccd095d9f590bbd95ddda279 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -780,7 +780,8 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
 {
        struct xe_device *xe = uc_fw_to_xe(uc_fw);
        struct xe_gt *gt = uc_fw_to_gt(uc_fw);
-       u32 src_offset, dma_ctrl;
+       u64 src_offset;
+       u32 dma_ctrl;
        int ret;
 
        xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);