+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree fragment for LS1028A QDS board, serdes 13bb
- *
- * Copyright 2019-2021 NXP
- *
- * Requires a LS1028A QDS board with lane B rework.
- * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
- * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
- */
-
-/dts-v1/;
-/plugin/;
-
-&mdio_slot1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- slot1_sgmii: ethernet-phy@2 {
- /* AQR112 */
- reg = <0x2>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-};
-
-&enetc_port0 {
- phy-handle = <&slot1_sgmii>;
- phy-mode = "usxgmii";
- managed = "in-band-status";
- status = "okay";
-};
-
-&mdio_slot2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* 4 ports on AQR412 */
- slot2_qxgmii0: ethernet-phy@0 {
- reg = <0x0>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-
- slot2_qxgmii1: ethernet-phy@1 {
- reg = <0x1>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-
- slot2_qxgmii2: ethernet-phy@2 {
- reg = <0x2>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-
- slot2_qxgmii3: ethernet-phy@3 {
- reg = <0x3>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-};
-
-&mscc_felix_ports {
- port@0 {
- status = "okay";
- phy-handle = <&slot2_qxgmii0>;
- phy-mode = "usxgmii";
- managed = "in-band-status";
- };
-
- port@1 {
- status = "okay";
- phy-handle = <&slot2_qxgmii1>;
- phy-mode = "usxgmii";
- managed = "in-band-status";
- };
-
- port@2 {
- status = "okay";
- phy-handle = <&slot2_qxgmii2>;
- phy-mode = "usxgmii";
- managed = "in-band-status";
- };
-
- port@3 {
- status = "okay";
- phy-handle = <&slot2_qxgmii3>;
- phy-mode = "usxgmii";
- managed = "in-band-status";
- };
-};
-
-&mscc_felix {
- status = "okay";
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 13bb
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
+ * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&mdio_slot1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&mdio_slot2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on AQR412 */
+ slot2_qxgmii0: ethernet-phy@0 {
+ reg = <0x0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii1: ethernet-phy@1 {
+ reg = <0x1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&mscc_felix_ports {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii0>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii1>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii2>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii3>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+};
+
+&mscc_felix {
+ status = "okay";
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree fragment for LS1028A QDS board, serdes 69xx
- *
- * Copyright 2019-2021 NXP
- *
- * Requires a LS1028A QDS board with lane B rework.
- * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
- */
-
-/dts-v1/;
-/plugin/;
-
-&mdio_slot1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- slot1_sgmii: ethernet-phy@2 {
- /* AQR112 */
- reg = <0x2>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-};
-
-&enetc_port0 {
- phy-handle = <&slot1_sgmii>;
- phy-mode = "2500base-x";
- status = "okay";
-};
-
-&mdio_slot2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* 4 ports on VSC8514 */
- slot2_qsgmii0: ethernet-phy@8 {
- reg = <0x8>;
- };
-
- slot2_qsgmii1: ethernet-phy@9 {
- reg = <0x9>;
- };
-
- slot2_qsgmii2: ethernet-phy@a {
- reg = <0xa>;
- };
-
- slot2_qsgmii3: ethernet-phy@b {
- reg = <0xb>;
- };
-};
-
-&mscc_felix_ports {
- port@0 {
- status = "okay";
- phy-handle = <&slot2_qsgmii0>;
- phy-mode = "qsgmii";
- managed = "in-band-status";
- };
-
- port@1 {
- status = "okay";
- phy-handle = <&slot2_qsgmii1>;
- phy-mode = "qsgmii";
- managed = "in-band-status";
- };
-
- port@2 {
- status = "okay";
- phy-handle = <&slot2_qsgmii2>;
- phy-mode = "qsgmii";
- managed = "in-band-status";
- };
-
- port@3 {
- status = "okay";
- phy-handle = <&slot2_qsgmii3>;
- phy-mode = "qsgmii";
- managed = "in-band-status";
- };
-};
-
-&mscc_felix {
- status = "okay";
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 69xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&mdio_slot1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "2500base-x";
+ status = "okay";
+};
+
+&mdio_slot2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on VSC8514 */
+ slot2_qsgmii0: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ slot2_qsgmii1: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ slot2_qsgmii2: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ slot2_qsgmii3: ethernet-phy@b {
+ reg = <0xb>;
+ };
+};
+
+&mscc_felix_ports {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii0>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii1>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii2>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii3>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+};
+
+&mscc_felix {
+ status = "okay";
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree fragment for LS1028A QDS board, serdes 7777
- *
- * Copyright 2019-2021 NXP
- *
- * Requires a LS1028A QDS board without lane B rework.
- * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
- * disabled, plugged in slot 1.
- */
-
-/dts-v1/;
-/plugin/;
-
-&mdio_slot1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* 4 ports on AQR412 */
- slot1_sxgmii0: ethernet-phy@0 {
- reg = <0x0>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-
- slot1_sxgmii1: ethernet-phy@1 {
- reg = <0x1>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-
- slot1_sxgmii2: ethernet-phy@2 {
- reg = <0x2>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-
- slot1_sxgmii3: ethernet-phy@3 {
- reg = <0x3>;
- compatible = "ethernet-phy-ieee802.3-c45";
- };
-};
-
-&mscc_felix_ports {
- port@0 {
- status = "okay";
- phy-handle = <&slot1_sxgmii0>;
- phy-mode = "2500base-x";
- };
-
- port@1 {
- status = "okay";
- phy-handle = <&slot1_sxgmii1>;
- phy-mode = "2500base-x";
- };
-
- port@2 {
- status = "okay";
- phy-handle = <&slot1_sxgmii2>;
- phy-mode = "2500base-x";
- };
-
- port@3 {
- status = "okay";
- phy-handle = <&slot1_sxgmii3>;
- phy-mode = "2500base-x";
- };
-};
-
-&mscc_felix {
- status = "okay";
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 7777
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
+ * disabled, plugged in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&mdio_slot1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on AQR412 */
+ slot1_sxgmii0: ethernet-phy@0 {
+ reg = <0x0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii1: ethernet-phy@1 {
+ reg = <0x1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&mscc_felix_ports {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii0>;
+ phy-mode = "2500base-x";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii1>;
+ phy-mode = "2500base-x";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii2>;
+ phy-mode = "2500base-x";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii3>;
+ phy-mode = "2500base-x";
+ };
+};
+
+&mscc_felix {
+ status = "okay";
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree fragment for LS1028A QDS board, serdes 85bb
- *
- * Copyright 2019-2021 NXP
- *
- * Requires a LS1028A QDS board with lane B rework.
- * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
- */
-
-/dts-v1/;
-/plugin/;
-
-&mdio_slot1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- slot1_sgmii: ethernet-phy@1c {
- /* 1st port on VSC8234 */
- reg = <0x1c>;
- };
-};
-
-&enetc_port0 {
- phy-handle = <&slot1_sgmii>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- status = "okay";
-};
-
-&mdio_slot2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* 4 ports on VSC8514 */
- slot2_qsgmii0: ethernet-phy@8 {
- reg = <0x8>;
- };
-
- slot2_qsgmii1: ethernet-phy@9 {
- reg = <0x9>;
- };
-
- slot2_qsgmii2: ethernet-phy@a {
- reg = <0xa>;
- };
-
- slot2_qsgmii3: ethernet-phy@b {
- reg = <0xb>;
- };
-};
-
-&mscc_felix_ports {
- port@0 {
- status = "okay";
- phy-handle = <&slot2_qsgmii0>;
- phy-mode = "qsgmii";
- managed = "in-band-status";
- };
-
- port@1 {
- status = "okay";
- phy-handle = <&slot2_qsgmii1>;
- phy-mode = "qsgmii";
- managed = "in-band-status";
- };
-
- port@2 {
- status = "okay";
- phy-handle = <&slot2_qsgmii2>;
- phy-mode = "qsgmii";
- managed = "in-band-status";
- };
-
- port@3 {
- status = "okay";
- phy-handle = <&slot2_qsgmii3>;
- phy-mode = "qsgmii";
- managed = "in-band-status";
- };
-};
-
-&mscc_felix {
- status = "okay";
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85bb
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&mdio_slot1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@1c {
+ /* 1st port on VSC8234 */
+ reg = <0x1c>;
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&mdio_slot2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on VSC8514 */
+ slot2_qsgmii0: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ slot2_qsgmii1: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ slot2_qsgmii2: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ slot2_qsgmii3: ethernet-phy@b {
+ reg = <0xb>;
+ };
+};
+
+&mscc_felix_ports {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii0>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii1>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii2>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii3>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+};
+
+&mscc_felix {
+ status = "okay";
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree fragment for LS1028A QDS board, serdes 85xx
- *
- * Copyright 2019-2021 NXP
- *
- * Requires a LS1028A QDS board without lane B rework.
- * Requires a SCH-24801 card in slot 1.
- */
-
-/dts-v1/;
-/plugin/;
-
-&mdio_slot1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* VSC8234 */
- slot1_sgmii0: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- slot1_sgmii1: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- slot1_sgmii2: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- slot1_sgmii3: ethernet-phy@1f {
- reg = <0x1f>;
- };
-};
-
-&enetc_port0 {
- phy-handle = <&slot1_sgmii0>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- status = "okay";
-};
-
-&mscc_felix_ports {
- port@1 {
- status = "okay";
- phy-handle = <&slot1_sgmii1>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- };
-
- port@2 {
- status = "okay";
- phy-handle = <&slot1_sgmii2>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- };
-};
-
-&mscc_felix {
- status = "okay";
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-24801 card in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&mdio_slot1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VSC8234 */
+ slot1_sgmii0: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ slot1_sgmii1: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ slot1_sgmii2: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ slot1_sgmii3: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&slot1_sgmii0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&mscc_felix_ports {
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii1>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii2>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+};
+
+&mscc_felix {
+ status = "okay";
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree fragment for LS1028A QDS board, serdes 85xx
- *
- * Copyright 2019-2021 NXP
- *
- * Requires a LS1028A QDS board without lane B rework.
- * Requires a SCH-24801 card in slot 1.
- */
-
-/dts-v1/;
-/plugin/;
-
-&mdio_slot1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* VSC8234 */
- slot1_sgmii0: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- slot1_sgmii1: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- slot1_sgmii2: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- slot1_sgmii3: ethernet-phy@1f {
- reg = <0x1f>;
- };
-};
-
-&mscc_felix_ports {
- port@0 {
- status = "okay";
- phy-handle = <&slot1_sgmii0>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- };
-
- port@1 {
- status = "okay";
- phy-handle = <&slot1_sgmii1>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- };
-
- port@2 {
- status = "okay";
- phy-handle = <&slot1_sgmii2>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- };
-
- port@3 {
- status = "okay";
- phy-handle = <&slot1_sgmii3>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- };
-};
-
-&mscc_felix {
- status = "okay";
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-24801 card in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&mdio_slot1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VSC8234 */
+ slot1_sgmii0: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ slot1_sgmii1: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ slot1_sgmii2: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ slot1_sgmii3: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
+
+&mscc_felix_ports {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii1>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii2>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii3>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+};
+
+&mscc_felix {
+ status = "okay";
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-#include "imx8mm-pinfunc.h"
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
-
- reg_cam: regulator-cam {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_cam>;
- compatible = "regulator-fixed";
- regulator-name = "reg_cam";
- gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- cam24m: cam24m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "cam24m";
- };
-};
-
-&csi {
- status = "okay";
-};
-
-&i2c3 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- imx219: sensor@10 {
- compatible = "sony,imx219";
- reg = <0x10>;
- clocks = <&cam24m>;
- VDIG-supply = <®_cam>;
-
- port {
- /* MIPI CSI-2 bus endpoint */
- imx219_to_mipi_csi2: endpoint {
- remote-endpoint = <&imx8mm_mipi_csi_in>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- link-frequencies = /bits/ 64 <456000000>;
- };
- };
- };
-};
-
-&mipi_csi {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- imx8mm_mipi_csi_in: endpoint {
- remote-endpoint = <&imx219_to_mipi_csi2>;
- data-lanes = <1 2>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- imx8mm_mipi_csi_out: endpoint {
- remote-endpoint = <&csi_in>;
- };
- };
- };
-};
-
-&iomuxc {
- pinctrl_reg_cam: regcamgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
+
+ reg_cam: regulator-cam {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_cam>;
+ compatible = "regulator-fixed";
+ regulator-name = "reg_cam";
+ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ cam24m: cam24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "cam24m";
+ };
+};
+
+&csi {
+ status = "okay";
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imx219: sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ clocks = <&cam24m>;
+ VDIG-supply = <®_cam>;
+
+ port {
+ /* MIPI CSI-2 bus endpoint */
+ imx219_to_mipi_csi2: endpoint {
+ remote-endpoint = <&imx8mm_mipi_csi_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+};
+
+&mipi_csi {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ imx8mm_mipi_csi_in: endpoint {
+ remote-endpoint = <&imx219_to_mipi_csi2>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ imx8mm_mipi_csi_out: endpoint {
+ remote-endpoint = <&csi_in>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_reg_cam: regcamgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41
+ >;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- *
- * GW72xx RS232 with RTS/CTS hardware flow control:
- * - GPIO4_0 rs485_en needs to be driven low (in-active)
- * - UART4_TX becomes RTS
- * - UART4_RX becomes CTS
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-#include "imx8mm-pinfunc.h"
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- compatible = "gw,imx8mm-gw72xx-0x";
-};
-
-&gpio4 {
- rs485_en {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "rs485_en";
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&uart4 {
- status = "disabled";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
- MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ *
+ * GW72xx RS232 with RTS/CTS hardware flow control:
+ * - GPIO4_0 rs485_en needs to be driven low (in-active)
+ * - UART4_TX becomes RTS
+ * - UART4_RX becomes CTS
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw72xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_en";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140
+ >;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- *
- * GW72xx RS422 (RS485 full duplex):
- * - GPIO1_0 rs485_term selects on-chip termination
- * - GPIO4_0 rs485_en needs to be driven high (active)
- * - GPIO4_2 rs485_hd needs to be driven low (in-active)
- * - UART4_TX is DE for RS485 transmitter
- * - RS485_EN needs to be pulled high
- * - RS485_HALF needs to be low
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-#include "imx8mm-pinfunc.h"
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- compatible = "gw,imx8mm-gw72xx-0x";
-};
-
-&gpio4 {
- rs485_en {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "rs485_en";
- };
-
- rs485_hd {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "rs485_hd";
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
- linux,rs485-enabled-at-boot-time;
- status = "okay";
-};
-
-&uart4 {
- status = "disabled";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ *
+ * GW72xx RS422 (RS485 full duplex):
+ * - GPIO1_0 rs485_term selects on-chip termination
+ * - GPIO4_0 rs485_en needs to be driven high (active)
+ * - GPIO4_2 rs485_hd needs to be driven low (in-active)
+ * - UART4_TX is DE for RS485 transmitter
+ * - RS485_EN needs to be pulled high
+ * - RS485_HALF needs to be low
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw72xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_en";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_hd";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ >;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- *
- * GW72xx RS485 HD:
- * - GPIO1_0 rs485_term selects on-chip termination
- * - GPIO4_0 rs485_en needs to be driven high (active)
- * - GPIO4_2 rs485_hd needs to be driven high (active)
- * - UART4_TX is DE for RS485 transmitter
- * - RS485_EN needs to be pulled high
- * - RS485_HALF needs to be pulled high
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-#include "imx8mm-pinfunc.h"
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- compatible = "gw,imx8mm-gw72xx-0x";
-};
-
-&gpio4 {
- rs485_en {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "rs485_en";
- };
-
- rs485_hd {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "rs485_hd";
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
- linux,rs485-enabled-at-boot-time;
- status = "okay";
-};
-
-&uart4 {
- status = "disabled";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ *
+ * GW72xx RS485 HD:
+ * - GPIO1_0 rs485_term selects on-chip termination
+ * - GPIO4_0 rs485_en needs to be driven high (active)
+ * - GPIO4_2 rs485_hd needs to be driven high (active)
+ * - UART4_TX is DE for RS485 transmitter
+ * - RS485_EN needs to be pulled high
+ * - RS485_HALF needs to be pulled high
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw72xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_en";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_hd";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ >;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-#include "imx8mm-pinfunc.h"
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
-
- reg_cam: regulator-cam {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_cam>;
- compatible = "regulator-fixed";
- regulator-name = "reg_cam";
- gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- cam24m: cam24m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "cam24m";
- };
-};
-
-&csi {
- status = "okay";
-};
-
-&i2c3 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- imx219: sensor@10 {
- compatible = "sony,imx219";
- reg = <0x10>;
- clocks = <&cam24m>;
- VDIG-supply = <®_cam>;
-
- port {
- /* MIPI CSI-2 bus endpoint */
- imx219_to_mipi_csi2: endpoint {
- remote-endpoint = <&imx8mm_mipi_csi_in>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- link-frequencies = /bits/ 64 <456000000>;
- };
- };
- };
-};
-
-&mipi_csi {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- imx8mm_mipi_csi_in: endpoint {
- remote-endpoint = <&imx219_to_mipi_csi2>;
- data-lanes = <1 2>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- imx8mm_mipi_csi_out: endpoint {
- remote-endpoint = <&csi_in>;
- };
- };
- };
-};
-
-&iomuxc {
- pinctrl_reg_cam: regcamgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
+
+ reg_cam: regulator-cam {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_cam>;
+ compatible = "regulator-fixed";
+ regulator-name = "reg_cam";
+ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ cam24m: cam24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "cam24m";
+ };
+};
+
+&csi {
+ status = "okay";
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imx219: sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ clocks = <&cam24m>;
+ VDIG-supply = <®_cam>;
+
+ port {
+ /* MIPI CSI-2 bus endpoint */
+ imx219_to_mipi_csi2: endpoint {
+ remote-endpoint = <&imx8mm_mipi_csi_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+};
+
+&mipi_csi {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ imx8mm_mipi_csi_in: endpoint {
+ remote-endpoint = <&imx219_to_mipi_csi2>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ imx8mm_mipi_csi_out: endpoint {
+ remote-endpoint = <&csi_in>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_reg_cam: regcamgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41
+ >;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- *
- * GW73xx RS232 with RTS/CTS hardware flow control:
- * - GPIO4_0 rs485_en needs to be driven low (in-active)
- * - UART4_TX becomes RTS
- * - UART4_RX becomes CTS
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-#include "imx8mm-pinfunc.h"
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- compatible = "gw,imx8mm-gw73xx-0x";
-};
-
-&gpio4 {
- rs485_en {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "rs485_en";
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&uart4 {
- status = "disabled";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
- MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ *
+ * GW73xx RS232 with RTS/CTS hardware flow control:
+ * - GPIO4_0 rs485_en needs to be driven low (in-active)
+ * - UART4_TX becomes RTS
+ * - UART4_RX becomes CTS
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw73xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_en";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140
+ >;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 Gateworks Corporation
- *
- * GW73xx RS422 (RS485 full duplex):
- * - GPIO1_0 rs485_term selects on-chip termination
- * - GPIO4_0 rs485_en needs to be driven high (active)
- * - GPIO4_2 rs485_hd needs to be driven low (in-active)
- * - UART4_TX is DE for RS485 transmitter
- * - RS485_EN needs to be pulled high
- * - RS485_HALF needs to be low
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-#include "imx8mm-pinfunc.h"
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- compatible = "gw,imx8mm-gw73xx-0x";
-};
-
-&gpio4 {
- rs485_en {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "rs485_en";
- };
-
- rs485_hd {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "rs485_hd";
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
- linux,rs485-enabled-at-boot-time;
- status = "okay";
-};
-
-&uart4 {
- status = "disabled";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Gateworks Corporation
+ *
+ * GW73xx RS422 (RS485 full duplex):
+ * - GPIO1_0 rs485_term selects on-chip termination
+ * - GPIO4_0 rs485_en needs to be driven high (active)
+ * - GPIO4_2 rs485_hd needs to be driven low (in-active)
+ * - UART4_TX is DE for RS485 transmitter
+ * - RS485_EN needs to be pulled high
+ * - RS485_HALF needs to be low
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw73xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_en";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_hd";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ >;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 Gateworks Corporation
- *
- * GW73xx RS485 HD:
- * - GPIO1_0 rs485_term selects on-chip termination
- * - GPIO4_0 rs485_en needs to be driven high (active)
- * - GPIO4_2 rs485_hd needs to be driven high (active)
- * - UART4_TX is DE for RS485 transmitter
- * - RS485_EN needs to be pulled high
- * - RS485_HALF needs to be pulled high
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-#include "imx8mm-pinfunc.h"
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
- compatible = "gw,imx8mm-gw73xx-0x";
-};
-
-&gpio4 {
- rs485_en {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "rs485_en";
- };
-
- rs485_hd {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "rs485_hd";
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
- linux,rs485-enabled-at-boot-time;
- status = "okay";
-};
-
-&uart4 {
- status = "disabled";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Gateworks Corporation
+ *
+ * GW73xx RS485 HD:
+ * - GPIO1_0 rs485_term selects on-chip termination
+ * - GPIO4_0 rs485_en needs to be driven high (active)
+ * - GPIO4_2 rs485_hd needs to be driven high (active)
+ * - UART4_TX is DE for RS485 transmitter
+ * - RS485_EN needs to be pulled high
+ * - RS485_HALF needs to be pulled high
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mm-gw73xx-0x";
+};
+
+&gpio4 {
+ rs485_en {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_en";
+ };
+
+ rs485_hd {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485_hd";
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
+ >;
+ };
+};
projects / linux.git / commitdiff