staging: r8188eu: remove ODM_SetRFReg()

ODM_SetRFReg() is just a wrapper around rtl8188e_PHY_SetRFReg().
Remove ODM_SetRFReg() and call rtl8188e_PHY_SetRFReg() directly.

Signed-off-by: Michael Straube <straube.linux@gmail.com>
Link: https://lore.kernel.org/r/20211229205108.26373-5-straube.linux@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c b/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c
index f6f99b2acc016f3aedd19e0d956ed1349f96d23c..8eec8ea95162d4f40bbc8e5bd2ff4f81ce1766b0 100644 (file)
--- a/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c
+++ b/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c
@@ -409,14 +409,14 @@ phy_PathA_RxIQK(struct adapter *adapt)
        /* 1 Get TXIMR setting */
        /* modify RXIQK mode table */
        ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B);
 
        /* PA,PAD off */
-       ODM_SetRFReg(dm_odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);
 
        ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
 
@@ -458,10 +458,10 @@ phy_PathA_RxIQK(struct adapter *adapt)
        /* 1 RX IQK */
        /* modify RXIQK mode table */
        ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);
        ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
 
        /* IQK setting */
@@ -492,7 +492,7 @@ phy_PathA_RxIQK(struct adapter *adapt)
 
        /* reload RF 0xdf */
        ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
 
        if (!(regeac & BIT(27)) &&              /* if Tx is OK, check whether Rx is OK */
            (((regEA4 & 0x03FF0000) >> 16) != 0x132) &&
@@ -839,8 +839,6 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
 {
        u8 tmpreg;
        u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;
-       struct hal_data_8188e *pHalData = &adapt->haldata;
-       struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
 
        /* Check continuous TX and Packet TX */
        tmpreg = rtw_read8(adapt, 0xd03);
@@ -861,18 +859,18 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
 
                /* 2. Set RF mode = standby mode */
                /* Path-A */
-               ODM_SetRFReg(dm_odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000);
+               rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000);
 
                /* Path-B */
                if (is2t)
-                       ODM_SetRFReg(dm_odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode & 0x8FFFF) | 0x10000);
+                       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode & 0x8FFFF) | 0x10000);
        }
 
        /* 3. Read RF reg18 */
        LC_Cal = rtl8188e_PHY_QueryRFReg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits);
 
        /* 4. Set LC calibration begin  bit15 */
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000);
+       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000);
 
        ODM_sleep_ms(100);
 
@@ -881,11 +879,11 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
                /* Deal with continuous TX case */
                /* Path-A */
                rtw_write8(adapt, 0xd03, tmpreg);
-               ODM_SetRFReg(dm_odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
+               rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
 
                /* Path-B */
                if (is2t)
-                       ODM_SetRFReg(dm_odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
+                       rtl8188e_PHY_SetRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
        } else {
                /*  Deal with Packet TX case */
                rtw_write8(adapt, REG_TXPAUSE, 0x00);

diff --git a/drivers/staging/r8188eu/hal/odm_RegConfig8188E.c b/drivers/staging/r8188eu/hal/odm_RegConfig8188E.c
index f75086d7c569013efc6675414e7cbe410dd59c2d..c5f424c89e360ed0262c1fae895f23da70355c43 100644 (file)
--- a/drivers/staging/r8188eu/hal/odm_RegConfig8188E.c
+++ b/drivers/staging/r8188eu/hal/odm_RegConfig8188E.c
@@ -20,7 +20,7 @@ void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
        } else if (Addr == 0xf9) {
                ODM_delay_us(1);
        } else {
-               ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
+               rtl8188e_PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
                /*  Add 1us delay between BB/RF register setting. */
                ODM_delay_us(1);
        }

diff --git a/drivers/staging/r8188eu/hal/odm_interface.c b/drivers/staging/r8188eu/hal/odm_interface.c
index bf82f40cca24f63ac1732b2cc3ecc4f1a02020f7..42d6485758c0407a3a1fb175b62ae1dc3028dd36 100644 (file)
--- a/drivers/staging/r8188eu/hal/odm_interface.c
+++ b/drivers/staging/r8188eu/hal/odm_interface.c
@@ -16,12 +16,6 @@ u32 ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask)
        return rtl8188e_PHY_QueryBBReg(Adapter, RegAddr, BitMask);
 }
 
-void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum rf_radio_path    eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
-{
-       struct adapter *Adapter = pDM_Odm->Adapter;
-       rtl8188e_PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, RegAddr, BitMask, Data);
-}
-
 /*  ODM Memory relative API. */
 s32 ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2, u32 length)
 {

diff --git a/drivers/staging/r8188eu/include/odm_interface.h b/drivers/staging/r8188eu/include/odm_interface.h
index aabc33927a307c1f464b65fb1d117efc55d1c68e..29bf5ae468da697fcdd8d54f653689a9b887c4f5 100644 (file)
--- a/drivers/staging/r8188eu/include/odm_interface.h
+++ b/drivers/staging/r8188eu/include/odm_interface.h
@@ -17,9 +17,6 @@ void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr,
 
 u32 ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask);
 
-void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum rf_radio_path eRFPath,
-                 u32 RegAddr, u32 BitMask, u32 Data);
-
 /*  Memory Relative Function. */
 s32 ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2,
                      u32 length);