arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes

Add the ufs controller node and phy node for gs101.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240430141445.2688499-3-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 9f7635a7928ecb3fa2965797fc90d641f03451a4..16e1c474e8dd4c76e1b73717b56d85bb0ef3326e 100644 (file)
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1332,6 +1332,42 @@
                        interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
                };
 
+               ufs_0: ufs@14700000 {
+                       compatible = "google,gs101-ufs";
+                       reg = <0x14700000 0x200>,
+                             <0x14701100 0x200>,
+                             <0x14780000 0xa000>,
+                             <0x14600000 0x100>;
+                       reg-names = "hci", "vs_hci", "unipro", "ufsp";
+                       interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+                       clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
+                                <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
+                                <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
+                                <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
+                                <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>,
+                                <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
+                       clock-names = "core_clk", "sclk_unipro_main", "fmp",
+                                     "aclk", "pclk", "sysreg";
+                       freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
+                       pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+                       pinctrl-names = "default";
+                       phys = <&ufs_0_phy>;
+                       phy-names = "ufs-phy";
+                       samsung,sysreg = <&sysreg_hsi2 0x710>;
+                       status = "disabled";
+               };
+
+               ufs_0_phy: phy@14704000 {
+                       compatible = "google,gs101-ufs-phy";
+                       reg = <0x14704000 0x3000>;
+                       reg-names = "phy-pma";
+                       samsung,pmu-syscon = <&pmu_system_controller>;
+                       #phy-cells = <0>;
+                       clocks = <&ext_24_5m>;
+                       clock-names = "ref_clk";
+                       status = "disabled";
+               };
+
                cmu_apm: clock-controller@17400000 {
                        compatible = "google,gs101-cmu-apm";
                        reg = <0x17400000 0x8000>;