#include "config-devices.h"
#include "e820_memory_layout.h"
#include "fw_cfg.h"
-
-/* debug PC/ISA interrupts */
-//#define DEBUG_IRQ
-
-#ifdef DEBUG_IRQ
-#define DPRINTF(fmt, ...) \
- do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...)
-#endif
+#include "trace.h"
GlobalProperty pc_compat_4_2[] = {};
const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
{
GSIState *s = opaque;
- DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
+ trace_pc_gsi_interrupt(n, level);
if (n < ISA_NUM_IRQS) {
qemu_set_irq(s->i8259_irq[n], level);
}
CPUState *cs = first_cpu;
X86CPU *cpu = X86_CPU(cs);
- DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
+ trace_pc_pic_interrupt(irq, level);
if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
CPU_FOREACH(cs) {
cpu = X86_CPU(cs);
Port92State *s = opaque;
int oldval = s->outport;
- DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
+ trace_port92_write(val);
s->outport = val;
qemu_set_irq(s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {
uint32_t ret;
ret = s->outport;
- DPRINTF("port92: read 0x%02x\n", ret);
+ trace_port92_read(ret);
return ret;
}
# vmport.c
vmport_register(unsigned char command, void *func, void *opaque) "command: 0x%02x func: %p opaque: %p"
vmport_command(unsigned char command) "command: 0x%02x"
+
+# pc.c
+pc_gsi_interrupt(int irqn, int level) "GSI interrupt #%d level:%d"
+pc_pic_interrupt(int irqn, int level) "PIC interrupt #%d level:%d"
+port92_read(uint8_t val) "port92: read 0x%02x"
+port92_write(uint8_t val) "port92: write 0x%02x"