powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_SHIFT_BUG
authorCédric Le Goater <clg@kaod.org>
Thu, 10 Dec 2020 17:14:45 +0000 (18:14 +0100)
committerMichael Ellerman <mpe@ellerman.id.au>
Thu, 10 Dec 2020 22:53:10 +0000 (09:53 +1100)
This flag was used to support the PHB4 LSIs on P9 DD1 and we have
stopped supporting this CPU when DD2 came out. See skiboot commit:

  https://github.com/open-power/skiboot/commit/0b0d15e3c170

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201210171450.1933725-9-clg@kaod.org
arch/powerpc/include/asm/opal-api.h
arch/powerpc/include/asm/xive.h
arch/powerpc/kvm/book3s_xive_native.c
arch/powerpc/kvm/book3s_xive_template.c
arch/powerpc/sysdev/xive/common.c
arch/powerpc/sysdev/xive/native.c

index 1dffa3cb16bacfe5786db2b57cf0c0b7ca044cf9..48ee604ca39ab8594bcdbf0ab80948a599dbfa9a 100644 (file)
@@ -1091,7 +1091,7 @@ enum {
        OPAL_XIVE_IRQ_TRIGGER_PAGE      = 0x00000001,
        OPAL_XIVE_IRQ_STORE_EOI         = 0x00000002,
        OPAL_XIVE_IRQ_LSI               = 0x00000004,
-       OPAL_XIVE_IRQ_SHIFT_BUG         = 0x00000008,
+       OPAL_XIVE_IRQ_SHIFT_BUG         = 0x00000008, /* P9 DD1.0 workaround */
        OPAL_XIVE_IRQ_MASK_VIA_FW       = 0x00000010,
        OPAL_XIVE_IRQ_EOI_VIA_FW        = 0x00000020,
 };
index d332dd9a18dea693d51fecf0aedaa8f2d56ed855..b3c039d0bb6ea0b2851c9061fbff23831cdcacce 100644 (file)
@@ -60,7 +60,7 @@ struct xive_irq_data {
 };
 #define XIVE_IRQ_FLAG_STORE_EOI        0x01
 #define XIVE_IRQ_FLAG_LSI      0x02
-#define XIVE_IRQ_FLAG_SHIFT_BUG        0x04
+/* #define XIVE_IRQ_FLAG_SHIFT_BUG     0x04 */ /* P9 DD1.0 workaround */
 #define XIVE_IRQ_FLAG_MASK_FW  0x08
 #define XIVE_IRQ_FLAG_EOI_FW   0x10
 #define XIVE_IRQ_FLAG_H_INT_ESB        0x20
index 7f120cf9c594ada38011334614ef1d4b031fd978..76800c84f2a35ae5ca871aef415a19db1b7b6ec0 100644 (file)
@@ -37,9 +37,6 @@ static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset)
         * ordering.
         */
 
-       if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
-               offset |= offset << 4;
-
        val = in_be64(xd->eoi_mmio + offset);
        return (u8)val;
 }
index 4ad3c027945813fe73f5141fe93eabb1ecf27407..ece36e024a8f89c386320ac02f7bfadf15be8ec6 100644 (file)
@@ -61,9 +61,6 @@ static u8 GLUE(X_PFX,esb_load)(struct xive_irq_data *xd, u32 offset)
        if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
                offset |= XIVE_ESB_LD_ST_MO;
 
-       if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
-               offset |= offset << 4;
-
        val =__x_readq(__x_eoi_page(xd) + offset);
 #ifdef __LITTLE_ENDIAN__
        val >>= 64-8;
index 61a5f08798e9be7de54b913fee7a9fc96af93003..8499d0b24c1d5071850fc419a579087b7c3bd10d 100644 (file)
@@ -200,10 +200,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
        if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
                offset |= XIVE_ESB_LD_ST_MO;
 
-       /* Handle HW errata */
-       if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
-               offset |= offset << 4;
-
        if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
                val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
        else
@@ -214,10 +210,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
 
 static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
 {
-       /* Handle HW errata */
-       if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
-               offset |= offset << 4;
-
        if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
                xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
        else
@@ -1312,7 +1304,6 @@ static const struct {
 } xive_irq_flags[] = {
        { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
        { XIVE_IRQ_FLAG_LSI,       "LSI"       },
-       { XIVE_IRQ_FLAG_SHIFT_BUG, "SHIFT_BUG" },
        { XIVE_IRQ_FLAG_MASK_FW,   "MASK_FW"   },
        { XIVE_IRQ_FLAG_EOI_FW,    "EOI_FW"    },
        { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
index c3182ec9ed6557173a058e9fc98899d53a1a26b9..f501b1640068b5d18a8b67d26e77a04d288eee9d 100644 (file)
@@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
                data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
        if (opal_flags & OPAL_XIVE_IRQ_LSI)
                data->flags |= XIVE_IRQ_FLAG_LSI;
-       if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
-               data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
        if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
                data->flags |= XIVE_IRQ_FLAG_MASK_FW;
        if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)