tcg: Add signed multiword multiplication operations

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

diff --git a/tcg/README b/tcg/README
index 89f0cdd3690d8dfdcba2afe8e2fadec754ab586b..934e7afc9656926b26aea7a0a2809f18613636c6 100644 (file)
--- a/tcg/README
+++ b/tcg/README
@@ -375,6 +375,10 @@ is returned in two single-word outputs.
 Similar to mul, except two unsigned inputs T1 and T2 yielding the full
 double-word product T0.  The later is returned in two single-word outputs.
 
+* muls2_i32/i64 t0_low, t0_high, t1, t2
+
+Similar to mulu2, except the two inputs T1 and T2 are signed.
+
 ********* 64-bit target on 32-bit host support
 
 The following opcodes are internal to TCG.  Thus they are to be implemented by

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 7083f3a700d44b19f4696394594737545e4ba778..f9599bd6879b425d529949f2719e0239dff71e67 100644 (file)
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -75,6 +75,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nor_i32          0
 #define TCG_TARGET_HAS_deposit_i32      0
 #define TCG_TARGET_HAS_movcond_i32      1
+#define TCG_TARGET_HAS_muls2_i32        0
 
 enum {
     TCG_AREG0 = TCG_REG_R6,

diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index e2754fe970bac811634da0962f088ed40ec28ae0..ebd53d9e3620bdcee65a5540694e238be77fdbf7 100644 (file)
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -98,6 +98,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nor_i32          0
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_movcond_i32      1
+#define TCG_TARGET_HAS_muls2_i32        0
 
 /* optional instructions automatically implemented */
 #define TCG_TARGET_HAS_neg_i32          0 /* sub rd, 0, rs */

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 4f0017101ada6ca667b4261af055a539bc80727b..2b08ef79bb0c6eb1cb6761b03f0de05eef28870b 100644 (file)
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -95,6 +95,7 @@ typedef enum {
 #define TCG_TARGET_HAS_add2_i32         1
 #define TCG_TARGET_HAS_sub2_i32         1
 #define TCG_TARGET_HAS_mulu2_i32        1
+#define TCG_TARGET_HAS_muls2_i32        0
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_div2_i64         1
@@ -120,6 +121,7 @@ typedef enum {
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
 #define TCG_TARGET_HAS_mulu2_i64        0
+#define TCG_TARGET_HAS_muls2_i64        0
 #endif
 
 #define TCG_TARGET_deposit_i32_valid(ofs, len) \

diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index 40f442ebe443436553b25affd2119f0012b23904..e3d72ea52f130cbed0288c9ad3f2745e50a351fe 100644 (file)
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -142,6 +142,8 @@ typedef enum {
 #define TCG_TARGET_HAS_sub2_i64         0
 #define TCG_TARGET_HAS_mulu2_i32        0
 #define TCG_TARGET_HAS_mulu2_i64        0
+#define TCG_TARGET_HAS_muls2_i32        0
+#define TCG_TARGET_HAS_muls2_i64        0
 
 #define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)
 #define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)

diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 78af664ccab4fce4df8718b86c11669456fdb8f3..0384bd384fc79b887b344cb898d44321bf51d1ee 100644 (file)
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -87,6 +87,7 @@ typedef enum {
 #define TCG_TARGET_HAS_orc_i32          0
 #define TCG_TARGET_HAS_eqv_i32          0
 #define TCG_TARGET_HAS_nand_i32         0
+#define TCG_TARGET_HAS_muls2_i32        0
 
 /* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \

diff --git a/tcg/optimize.c b/tcg/optimize.c
index 027b3a53e6a716b7f1de0af04bc0adcfe9b08c3d..bc6e5c16a9146215ebe00fd297793fedaf361676 100644 (file)
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -559,6 +559,7 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr,
             swap_commutative(args[1], &args[3], &args[5]);
             break;
         CASE_OP_32_64(mulu2):
+        CASE_OP_32_64(muls2):
             swap_commutative(args[0], &args[2], &args[3]);
             break;
         case INDEX_op_brcond2_i32:

diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 0fdad04ee4d3cb69e4c6d705e3ff138029f5862c..17a6bb367a4498bc68e3e135866ce5af31a9c4c0 100644 (file)
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -94,6 +94,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nor_i32          1
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_movcond_i32      1
+#define TCG_TARGET_HAS_muls2_i32        0
 
 #define TCG_AREG0 TCG_REG_R27
 

diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 86929c18ce145fd84661ee1a456066549e662ca2..aa6a0f0306f4a51f664451ceff05910d48ec738d 100644 (file)
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -88,6 +88,7 @@ typedef enum {
 #define TCG_TARGET_HAS_add2_i32         0
 #define TCG_TARGET_HAS_sub2_i32         0
 #define TCG_TARGET_HAS_mulu2_i32        0
+#define TCG_TARGET_HAS_muls2_i32        0
 
 #define TCG_TARGET_HAS_div_i64          1
 #define TCG_TARGET_HAS_rot_i64          0
@@ -112,6 +113,7 @@ typedef enum {
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
 #define TCG_TARGET_HAS_mulu2_i64        0
+#define TCG_TARGET_HAS_muls2_i64        0
 
 #define TCG_AREG0 TCG_REG_R27
 

diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index ee31c37bdb60dbebd4c9f633ef7d6e736be40e03..40211e68f10b9bc0d3bba425a02ae5ab648f439f 100644 (file)
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -68,6 +68,7 @@ typedef enum TCGReg {
 #define TCG_TARGET_HAS_add2_i32         0
 #define TCG_TARGET_HAS_sub2_i32         0
 #define TCG_TARGET_HAS_mulu2_i32        0
+#define TCG_TARGET_HAS_muls2_i32        0
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_div2_i64         1
@@ -93,6 +94,7 @@ typedef enum TCGReg {
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
 #define TCG_TARGET_HAS_mulu2_i64        0
+#define TCG_TARGET_HAS_muls2_i64        0
 #endif
 
 /* used for function call generation */

diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index e440ad2190470c2ea005668de9e06191ad81ef66..b5217bef25e641557144cf6abd5c7618372121b4 100644 (file)
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -105,6 +105,7 @@ typedef enum {
 #define TCG_TARGET_HAS_add2_i32         1
 #define TCG_TARGET_HAS_sub2_i32         1
 #define TCG_TARGET_HAS_mulu2_i32        1
+#define TCG_TARGET_HAS_muls2_i32        0
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_div_i64          1
@@ -130,6 +131,7 @@ typedef enum {
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
 #define TCG_TARGET_HAS_mulu2_i64        0
+#define TCG_TARGET_HAS_muls2_i64        0
 #endif
 
 #define TCG_AREG0 TCG_REG_I0

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index e93698e3d0ae575751a397acbd28cd866ee8adfd..4246e9c1fa6296c8f5e9ffac45e4593310c0a7e8 100644 (file)
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -86,6 +86,7 @@ DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
 DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
 DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
 DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
+DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
 DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
 
@@ -161,6 +162,7 @@ DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
 DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
+DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
 
 /* QEMU specific */
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS

diff --git a/tcg/tcg.h b/tcg/tcg.h
index 255cbdb473da3dbf9edde4f0e685b296cbfc6351..b195396b0ff06145e5746e0b71e6464abc99a68d 100644 (file)
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -83,6 +83,7 @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
 #define TCG_TARGET_HAS_mulu2_i64        0
+#define TCG_TARGET_HAS_muls2_i64        0
 /* Turn some undef macros into true macros.  */
 #define TCG_TARGET_HAS_add2_i32         1
 #define TCG_TARGET_HAS_sub2_i32         1

diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 5986da26aa945b6b88c6f42c58ebead63ac6f11a..1f17576f549c1990d3b1b41a958e34c37382a3a4 100644 (file)
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -76,6 +76,7 @@
 #define TCG_TARGET_HAS_orc_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_movcond_i32      0
+#define TCG_TARGET_HAS_muls2_i32        0
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_bswap16_i64      1
@@ -100,6 +101,7 @@
 #define TCG_TARGET_HAS_orc_i64          0
 #define TCG_TARGET_HAS_rot_i64          1
 #define TCG_TARGET_HAS_movcond_i64      0
+#define TCG_TARGET_HAS_muls2_i64        0
 
 #define TCG_TARGET_HAS_add2_i32         0
 #define TCG_TARGET_HAS_sub2_i32         0