media: hantro: postproc: Fix legacy regs configuration

Some postproc legacy registers were set in VP9 code. Move them to
postproc and fix their value.

Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
index 91c21b634fab1ec0cb11ee3401c4946211914080..c9cb11fd95af73463984d7e33d4f2fee8d339725 100644 (file)
--- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
@@ -515,16 +515,8 @@ static void
 config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params)
 {
        if (ctx->dev->variant->legacy_regs) {
-               u8 pp_shift = 0;
-
                hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth);
                hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth);
-               hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth);
-
-               if (dec_params->bit_depth > 8)
-                       pp_shift = 16 - dec_params->bit_depth;
-
-               hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift);
                hantro_reg_write(ctx->dev, &g2_pix_shift, 0);
        } else {
                hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8);

diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
index b77cc55e43eaee973e26650f19d2b1bfb64b4f7e..8933b4af73edbd3b44b8db62484c8189d2a35d29 100644 (file)
--- a/drivers/staging/media/hantro/hantro_postproc.c
+++ b/drivers/staging/media/hantro/hantro_postproc.c
@@ -130,6 +130,16 @@ static void hantro_postproc_g2_enable(struct hantro_ctx *ctx)
                hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);
                hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset);
        }
+       if (ctx->dev->variant->legacy_regs) {
+               int out_depth = hantro_get_format_depth(ctx->dst_fmt.pixelformat);
+               u8 pp_shift = 0;
+
+               if (out_depth > 8)
+                       pp_shift = 16 - out_depth;
+
+               hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, out_depth);
+               hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift);
+       }
        hantro_reg_write(vpu, &g2_out_rs_e, 1);
 }