drm/xe/dg2: Drop pre-production workarounds

Pre-production hardware is anything before C0 (for DG2-G10), before B1
(for DG2-G11), or before A1 (for DG2-G12).  Workarounds specific to such
hardware was already removed from i915 in commit eaeb4b361452
("drm/i915/dg2: Drop pre-production GT workarounds") and there's even
less value keeping these around in the Xe driver.

v2:
 - Drop Wa_14011441408 from xe_mocs.c.  (Gustavo)
 - Drop Wa_14010648519, Wa_14010198302, and Wa_1608949956 which were
   mis-implemented; they were only supposed to apply to early steppings
   of DG2-G10, but were being applied unconditionally on all DG2.
   (Gustavo)
 - Drop reference to Wa_16011620976; the implementation stays because it
   still matches Wa_22015475538.  (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231215214531.2576215-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 482cb0df9f15bc28d9f5c2a0ea194319f1b2a21a..76b31d542e1ae546bb42190f07789ffbe30b56f4 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -133,13 +133,10 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
        if (XE_WA(gt, 22012773006))
                flags |= GUC_WA_POLLCS;
 
-       if (XE_WA(gt, 16011759253))
-               flags |= GUC_WA_GAM_CREDITS;
-
        if (XE_WA(gt, 14014475959))
                flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
-       if (XE_WA(gt, 22011391025) || XE_WA(gt, 14012197797))
+       if (XE_WA(gt, 22011391025))
                flags |= GUC_WA_DUAL_QUEUE;
 
        /*
@@ -150,9 +147,6 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
        if (GRAPHICS_VERx100(xe) < 1270)
                flags |= GUC_WA_PRE_PARSER;
 
-       if (XE_WA(gt, 16011777198))
-               flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
-
        if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685))
                flags |= GUC_WA_CONTEXT_ISOLATION;
 

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index ef79552e4f2fe19e72ea1ad23bc7b17b66d3e644..d205d684d8090368e85bcbeed4ac82f09d8a41eb 100644 (file)
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -290,18 +290,6 @@ static const struct xe_mocs_entry dg2_mocs_desc[] = {
        MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
 };
 
-static const struct xe_mocs_entry dg2_mocs_desc_g10_ax[] = {
-       /* Wa_14011441408: Set Go to Memory for MOCS#0 */
-       MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
-       /* UC - Coherent; GO:Memory */
-       MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
-       /* UC - Non-Coherent; GO:Memory */
-       MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
-
-       /* WB - LC */
-       MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
-};
-
 static const struct xe_mocs_entry pvc_mocs_desc[] = {
        /* Error */
        MOCS_ENTRY(0, 0, L3_3_WB),
@@ -409,15 +397,8 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
                info->unused_entries_index = 1;
                break;
        case XE_DG2:
-               if (xe->info.subplatform == XE_SUBPLATFORM_DG2_G10 &&
-                   xe->info.step.graphics >= STEP_A0 &&
-                   xe->info.step.graphics <= STEP_B0) {
-                       info->size = ARRAY_SIZE(dg2_mocs_desc_g10_ax);
-                       info->table = dg2_mocs_desc_g10_ax;
-               } else {
-                       info->size = ARRAY_SIZE(dg2_mocs_desc);
-                       info->table = dg2_mocs_desc;
-               }
+               info->size = ARRAY_SIZE(dg2_mocs_desc);
+               info->table = dg2_mocs_desc;
                info->uc_index = 1;
                info->n_entries = XELP_NUM_MOCS_ENTRIES;
                info->unused_entries_index = 3;

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 5f61dd87c58688f298a4e3f72eae7bafdba38601..7d6b86d602c8a7552af418f0d9820910e737b38c 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -125,13 +125,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 
        /* DG2 */
 
-       { XE_RTP_NAME("16010515920"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10),
-                      GRAPHICS_STEP(A0, B0),
-                      ENGINE_CLASS(VIDEO_DECODE)),
-         XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS)),
-         XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-       },
        { XE_RTP_NAME("22010523718"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
          XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
@@ -140,61 +133,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
          XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
          XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
        },
-       { XE_RTP_NAME("14012362059"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))
-       },
-       { XE_RTP_NAME("14012362059"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))
-       },
-       { XE_RTP_NAME("14010948348"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS))
-       },
-       { XE_RTP_NAME("14011037102"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(UNSLCGCTL9444, LTCDD_CLKGATE_DIS))
-       },
-       { XE_RTP_NAME("14011371254"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS))
-       },
-       { XE_RTP_NAME("14011431319"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(UNSLCGCTL9440,
-                            GAMTLBOACS_CLKGATE_DIS |
-                            GAMTLBVDBOX7_CLKGATE_DIS | GAMTLBVDBOX6_CLKGATE_DIS |
-                            GAMTLBVDBOX5_CLKGATE_DIS | GAMTLBVDBOX4_CLKGATE_DIS |
-                            GAMTLBVDBOX3_CLKGATE_DIS | GAMTLBVDBOX2_CLKGATE_DIS |
-                            GAMTLBVDBOX1_CLKGATE_DIS | GAMTLBVDBOX0_CLKGATE_DIS |
-                            GAMTLBKCR_CLKGATE_DIS | GAMTLBGUC_CLKGATE_DIS |
-                            GAMTLBBLT_CLKGATE_DIS),
-                        SET(UNSLCGCTL9444,
-                            GAMTLBGFXA0_CLKGATE_DIS | GAMTLBGFXA1_CLKGATE_DIS |
-                            GAMTLBCOMPA0_CLKGATE_DIS | GAMTLBCOMPA1_CLKGATE_DIS |
-                            GAMTLBCOMPB0_CLKGATE_DIS | GAMTLBCOMPB1_CLKGATE_DIS |
-                            GAMTLBCOMPC0_CLKGATE_DIS | GAMTLBCOMPC1_CLKGATE_DIS |
-                            GAMTLBCOMPD0_CLKGATE_DIS | GAMTLBCOMPD1_CLKGATE_DIS |
-                            GAMTLBMERT_CLKGATE_DIS |
-                            GAMTLBVEBOX3_CLKGATE_DIS | GAMTLBVEBOX2_CLKGATE_DIS |
-                            GAMTLBVEBOX1_CLKGATE_DIS | GAMTLBVEBOX0_CLKGATE_DIS))
-       },
-       { XE_RTP_NAME("14010569222"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, GAMEDIA_CLKGATE_DIS))
-       },
-       { XE_RTP_NAME("14011028019"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(SSMCGCTL9530, RTFUNIT_CLKGATE_DIS))
-       },
-       { XE_RTP_NAME("14010680813"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(XEHP_GAMSTLB_CTRL,
-                            CONTROL_BLOCK_CLKGATE_DIS |
-                            EGRESS_BLOCK_CLKGATE_DIS |
-                            TAG_BLOCK_CLKGATE_DIS))
-       },
        { XE_RTP_NAME("14014830051"),
          XE_RTP_RULES(PLATFORM(DG2)),
          XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
@@ -212,10 +150,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
                             INVALIDATION_BROADCAST_MODE_DIS |
                             GLOBAL_INVALIDATION_MODE))
        },
-       { XE_RTP_NAME("14010648519"),
-         XE_RTP_RULES(PLATFORM(DG2)),
-         XE_RTP_ACTIONS(SET(XEHP_L3NODEARBCFG, XEHP_LNESPARE))
-       },
 
        /* PVC */
 
@@ -376,13 +310,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
          XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
                             POLYGON_TRIFAN_LINELOOP_DISABLE))
        },
-       { XE_RTP_NAME("22012826095, 22013059131"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
-                      FUNC(xe_rtp_match_first_render_or_compute)),
-         XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
-                                  MAXREQS_PER_BANK,
-                                  REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
-       },
        { XE_RTP_NAME("22012826095, 22013059131"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G11),
                       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -390,28 +317,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                                   MAXREQS_PER_BANK,
                                   REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
        },
-       { XE_RTP_NAME("22013059131"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
-                      FUNC(xe_rtp_match_first_render_or_compute)),
-         XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
-       },
        { XE_RTP_NAME("22013059131"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G11),
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
        },
-       { XE_RTP_NAME("14010918519"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
-                      FUNC(xe_rtp_match_first_render_or_compute)),
-         XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
-                            FORCE_SLM_FENCE_SCOPE_TO_TILE |
-                            FORCE_UGM_FENCE_SCOPE_TO_TILE,
-                            /*
-                             * Ignore read back as it always returns 0 in these
-                             * steps
-                             */
-                            .read_mask = 0))
-       },
        { XE_RTP_NAME("14015227452"),
          XE_RTP_RULES(PLATFORM(DG2),
                       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -428,21 +338,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
        },
-       { XE_RTP_NAME("16011620976, 22015475538"),
+       { XE_RTP_NAME("22015475538"),
          XE_RTP_RULES(PLATFORM(DG2),
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
        },
-       { XE_RTP_NAME("22012654132"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0),
-                      FUNC(xe_rtp_match_first_render_or_compute)),
-         XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
-                            /*
-                             * Register can't be read back for verification on
-                             * DG2 due to Wa_14012342262
-                             */
-                            .read_mask = 0))
-       },
        { XE_RTP_NAME("22012654132"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G11),
                       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -461,68 +361,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
          XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
        },
-       { XE_RTP_NAME("14013392000"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE))
-       },
-       { XE_RTP_NAME("14012419201"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
-                            DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
-       },
-       { XE_RTP_NAME("14012419201"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
-                            DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
-       },
-       { XE_RTP_NAME("1308578152"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
-                      ENGINE_CLASS(RENDER),
-                      FUNC(xe_rtp_match_first_gslice_fused_off)),
-         XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1(RENDER_RING_BASE),
-                            REPLAY_MODE_GRANULARITY))
-       },
        { XE_RTP_NAME("22010960976, 14013347512"),
          XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
                             LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
        },
-       { XE_RTP_NAME("1608949956, 14010198302"),
-         XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(ROW_CHICKEN,
-                            MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE))
-       },
-       { XE_RTP_NAME("22010430635"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
-                            DISABLE_GRF_CLEAR))
-       },
-       { XE_RTP_NAME("14013202645"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
-       },
-       { XE_RTP_NAME("14013202645"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
-       },
-       { XE_RTP_NAME("22012532006"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
-                            DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
-       },
-       { XE_RTP_NAME("22012532006"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
-                            DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
-       },
        { XE_RTP_NAME("14015150844"),
          XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
@@ -652,21 +495,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 
        /* DG2 */
 
-       { XE_RTP_NAME("16011186671"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH),
-                        SET(VFLSKPD, DIS_OVER_FETCH_CACHE))
-       },
-       { XE_RTP_NAME("14010469329"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
-                            XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE))
-       },
-       { XE_RTP_NAME("14010698770, 22010613112, 22010465075"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
-                            DISABLE_CPS_AWARE_COLOR_PIPE))
-       },
        { XE_RTP_NAME("16013271637"),
          XE_RTP_RULES(PLATFORM(DG2)),
          XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,

diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 727bdc42921249a342e279b34156cd235535db82..e73b84e01ea1be588dbfda2f45d52948af0ee485 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -1,13 +1,8 @@
 22012773006    GRAPHICS_VERSION_RANGE(1200, 1250)
-16011759253    SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)
 14014475959    GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)
                PLATFORM(DG2)
 22011391025    PLATFORM(DG2)
-14012197797    PLATFORM(DG2), GRAPHICS_STEP(A0, B0)
-16011777198    SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0)
-               SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)
-22012727170    SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0)
-               SUBPLATFORM(DG2, G11)
+22012727170    SUBPLATFORM(DG2, G11)
 22012727685    SUBPLATFORM(DG2, G11)
 16015675438    PLATFORM(PVC)
                SUBPLATFORM(DG2, G10)