arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
authorPrasad Malisetty <pmaliset@codeaurora.org>
Thu, 7 Oct 2021 17:48:41 +0000 (23:18 +0530)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Sun, 24 Oct 2021 18:04:03 +0000 (13:04 -0500)
Enable PCIe controller and PHY for sc7280 IDP board.
Add specific NVMe GPIO entries for SKU1 and SKU2 support.

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1633628923-25047-4-git-send-email-pmaliset@codeaurora.org
arch/arm64/boot/dts/qcom/sc7280-idp.dts
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
arch/arm64/boot/dts/qcom/sc7280-idp2.dts

index e11412bae73804a13fbcdc93777b40107a0a18d6..9b991ba5daaf00570b85f49ea799a5b5b5b31a28 100644 (file)
        status = "okay";
 };
 
+&nvme_pwren {
+       pins = "gpio19";
+};
+
+&nvme_3v3_regulator {
+       gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+};
+
 &pmk8350_vadc {
        pmr735a_die_temp {
                reg = <PMR735A_ADC7_DIE_TEMP>;
index 272d5ca957dc77397eaac35218069feafee2ecf3..d623d71d8bd476e0eab6b6218c0cb56e1485d3ff 100644 (file)
                        linux,can-disable;
                };
        };
+
+       nvme_3v3_regulator: nvme-3v3-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "VLDO_3V3";
+
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               enable-active-high;
+               pinctrl-names = "default";
+               pinctrl-0 = <&nvme_pwren>;
+       };
 };
 
 /*
        modem-init;
 };
 
+&pcie1 {
+       status = "okay";
+       perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
+
+       vddpe-3v3-supply = <&nvme_3v3_regulator>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
+};
+
+&pcie1_phy {
+       status = "okay";
+
+       vdda-phy-supply = <&vreg_l10c_0p8>;
+       vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
 &pmk8350_vadc {
        pmk8350_die_temp {
                reg = <PMK8350_ADC7_DIE_TEMP>;
 };
 
 &tlmm {
+       nvme_pwren: nvme-pwren {
+               function = "gpio";
+       };
+
+       pcie1_reset_n: pcie1-reset-n {
+               pins = "gpio2";
+               function = "gpio";
+
+               drive-strength = <16>;
+               output-low;
+               bias-disable;
+       };
+
+       pcie1_wake_n: pcie1-wake-n {
+               pins = "gpio3";
+               function = "gpio";
+
+               drive-strength = <2>;
+               bias-pull-up;
+       };
+
        qup_uart7_sleep_cts: qup-uart7-sleep-cts {
                pins = "gpio28";
                function = "gpio";
index 1fc2addc8ab645755f4cf1ca86eee58dd01819ec..3ae99697d89326c09c98b2aa8e72e7c49dddcebd 100644 (file)
                stdout-path = "serial0:115200n8";
        };
 };
+
+&nvme_pwren {
+       pins = "gpio51";
+};
+
+&nvme_3v3_regulator {
+       gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+};