ctx->dc->debug.disable_dpp_power_gate = false;
ctx->dc->debug.disable_hubp_power_gate = false;
ctx->dc->debug.disable_dsc_power_gate = false;
+ ctx->dc->debug.disable_hpo_power_gate = false;
} else {
/*let's reset the config control flag*/
ctx->dc->config.disable_ips = 1; /*pmfw not support it, disable it all*/
result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
ASSERT(result == VBIOSSMC_Result_OK);
+ if (result != VBIOSSMC_Result_OK) {
+ DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
-
- if (result == VBIOSSMC_Status_BUSY) {
- smu_print("SMU response after wait: %d\n", result);
- return -1;
+ if (result == VBIOSSMC_Status_BUSY)
+ return -1;
}
/* First clear response register */
else
ASSERT(0);
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
- smu_print("SMU response after wait: %d\n", result);
+ DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
return -1;
}
ASSERT(0);
result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
//dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
- smu_print("SMU response after wait: %d\n", result);
+ DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
}
return REG_READ(MP1_SMN_C2PMSG_83);
bool disable_hubp_power_gate;
bool disable_dsc_power_gate;
bool disable_optc_power_gate;
+ bool disable_hpo_power_gate;
int dsc_min_slice_height_override;
int dsc_bpp_increment_div;
bool disable_pplib_wm_range;