drm/amdgpu: Add support for querying the max ibs in a submission. (v3)

This info would be used by radv to figure out when we need to
split a submission into multiple submissions. radv currently has
a limit of 192 which seems to work for most gfx submissions, but
is way too high for e.g. compute or sdma.

Userspace is available at
https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3

v3: Completely rewrote based on suggestion of making it a separate query.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 0efb38539d70cc6dff5da3e222cf3b4a2ac3a25f..1a2e342af1c0943c805e09e38a654ba68cf65d58 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1140,6 +1140,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                kfree(caps);
                return r;
        }
+       case AMDGPU_INFO_MAX_IBS: {
+               uint32_t max_ibs[AMDGPU_HW_IP_NUM];
+
+               for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
+                       max_ibs[i] = amdgpu_ring_max_ibs(i);
+
+               return copy_to_user(out, max_ibs,
+                                   min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
+       }
        default:
                DRM_DEBUG_KMS("Invalid request %d\n", info->query);
                return -EINVAL;

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index b6eb90df5d052d997f09c55b276e62b198ee36a8..6981e59a940177097c613bf24ed6d473c70b7b0e 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -876,6 +876,8 @@ struct drm_amdgpu_cs_chunk_data {
        #define AMDGPU_INFO_VIDEO_CAPS_DECODE           0
        /* Subquery id: Encode */
        #define AMDGPU_INFO_VIDEO_CAPS_ENCODE           1
+/* Query the max number of IBs per gang per submission */
+#define AMDGPU_INFO_MAX_IBS                    0x22
 
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK  0xff