if (!devpriv->mite && reg < 8) {
                        ni_writew(dev, data, reg * 2);
                } else {
-                       ni_writew(dev, reg, Window_Address);
-                       ni_writew(dev, data, Window_Data);
+                       ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
+                       ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
                }
                spin_unlock_irqrestore(&devpriv->window_lock, flags);
        }
                if (!devpriv->mite && reg < 8) {
                        val = ni_readw(dev, reg * 2);
                } else {
-                       ni_writew(dev, reg, Window_Address);
-                       val = ni_readw(dev, Window_Data);
+                       ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
+                       val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
                }
                spin_unlock_irqrestore(&devpriv->window_lock, flags);
        }
 
 #define NISTC_AI_SI_SAVE_REG           64
 #define NISTC_AI_SC_SAVE_REG           66
 
-/* Additional windowed registers unique to E series */
-
-/* 16 bit registers shadowed from DAQ-STC */
-#define Window_Address                 0x00
-#define Window_Data                    0x02
+/*
+ * PCI E Series Registers
+ */
+#define NI_E_STC_WINDOW_ADDR_REG       0x00    /* rw16 */
+#define NI_E_STC_WINDOW_DATA_REG       0x02    /* rw16 */
 
 /* i/o port offsets */