i40e: add description and modify interrupts configuration procedure

Add description for values written into registers QINT_XXXX
and small cosmetic changes for MSI/LEGACY interrupts
configuration in the same way as for MSI-X.
Descriptions confirm the code is written correctly and
make the code clear. Small cosmetic changes for MSI/LEGACY
interrupts make code clear in the same manner as for MSI-X
interrupts.

Signed-off-by: Jaroslaw Gawin <jaroslawx.gawin@intel.com>
Signed-off-by: Andrii Staikov <andrii.staikov@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>

diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h
index d86b6d349ea9d5bc5b4c3e62e86a4fab0a8fa31d..9a60d6b207f7ce10b4ec77a5abebc5f7f417aa11 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e.h
+++ b/drivers/net/ethernet/intel/i40e/i40e.h
@@ -399,6 +399,20 @@ struct i40e_ddp_old_profile_list {
                                 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
                                 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
 
+#define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \
+       (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \
+       (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \
+       ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \
+       ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \
+       (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT))
+
+#define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
+       (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
+       (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
+       ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
+       ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
+       (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
+
 struct i40e_flex_pit {
        struct list_head list;
        u16 src_offset;

diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 89dd46130c03fc5af0cdbd03594a866f2935fa2b..9b2f18dfd0c48b8c733cddc128d6217806e70c19 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -3879,7 +3879,7 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
                wr32(hw, I40E_PFINT_RATEN(vector - 1),
                     i40e_intrl_usec_to_reg(vsi->int_rate_limit));
 
-               /* Linked list for the queuepairs assigned to this vector */
+               /* begin of linked list for RX queue assigned to this vector */
                wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
                for (q = 0; q < q_vector->num_ringpairs; q++) {
                        u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs : qp;
@@ -3895,6 +3895,7 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
                        wr32(hw, I40E_QINT_RQCTL(qp), val);
 
                        if (has_xdp) {
+                               /* TX queue with next queue set to TX */
                                val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
                                      (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
                                      (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
@@ -3904,7 +3905,7 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
 
                                wr32(hw, I40E_QINT_TQCTL(nextqp), val);
                        }
-
+                       /* TX queue with next RX or end of linked list */
                        val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
                              (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
                              (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
@@ -3973,7 +3974,6 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
        struct i40e_q_vector *q_vector = vsi->q_vectors[0];
        struct i40e_pf *pf = vsi->back;
        struct i40e_hw *hw = &pf->hw;
-       u32 val;
 
        /* set the ITR configuration */
        q_vector->rx.next_update = jiffies + 1;
@@ -3990,28 +3990,20 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
        /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
        wr32(hw, I40E_PFINT_LNKLST0, 0);
 
-       /* Associate the queue pair to the vector and enable the queue int */
-       val = I40E_QINT_RQCTL_CAUSE_ENA_MASK                   |
-             (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT)  |
-             (nextqp      << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
-             (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
-
-       wr32(hw, I40E_QINT_RQCTL(0), val);
+       /* Associate the queue pair to the vector and enable the queue
+        * interrupt RX queue in linked list with next queue set to TX
+        */
+       wr32(hw, I40E_QINT_RQCTL(0), I40E_QINT_RQCTL_VAL(nextqp, 0, TX));
 
        if (i40e_enabled_xdp_vsi(vsi)) {
-               val = I40E_QINT_TQCTL_CAUSE_ENA_MASK                 |
-                     (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)|
-                     (I40E_QUEUE_TYPE_TX
-                      << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
-
-               wr32(hw, I40E_QINT_TQCTL(nextqp), val);
+               /* TX queue in linked list with next queue set to TX */
+               wr32(hw, I40E_QINT_TQCTL(nextqp),
+                    I40E_QINT_TQCTL_VAL(nextqp, 0, TX));
        }
 
-       val = I40E_QINT_TQCTL_CAUSE_ENA_MASK                  |
-             (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
-             (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
-
-       wr32(hw, I40E_QINT_TQCTL(0), val);
+       /* last TX queue so the next RX queue doesn't matter */
+       wr32(hw, I40E_QINT_TQCTL(0),
+            I40E_QINT_TQCTL_VAL(I40E_QUEUE_END_OF_LIST, 0, RX));
        i40e_flush(hw);
 }