drm/amdgpu: enable HDP clock gatting

Enabe HDP SD/DS clock gatting in Renoir series.

Signed-off-by: Prike.Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3cd98c144bc65d12adf818d626eb0a04fffa8ce7..3c3a7adad02494c719f504eb85c7fbce8796ee6a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1452,7 +1452,8 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable
        uint32_t def, data;
 
        if (adev->asic_type == CHIP_VEGA20 ||
-               adev->asic_type == CHIP_ARCTURUS) {
+               adev->asic_type == CHIP_ARCTURUS ||
+               adev->asic_type == CHIP_RENOIR) {
                def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
 
                if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))