arm64: dts: qcom: sc8280xp-crd: Add QMP to SuperSpeed graph

With support for the QMP combo phy to react to USB Type-C switch events,
introduce it as the next hop for the SuperSpeed lanes of the two USB
Type-C connectors, and connect the output of the DisplayPort controller
to the QMP combo phy.

This allows the TCPM to perform orientation switching of both USB and
DisplayPort signals.

Tested-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450
Tested-by: Johan Hovold <johan+linaro@kernel.org>	# X13s
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230515032743.400170-8-quic_bjorande@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 5b25d54b959115e3e18f19c90886e4d41bdafc5c..e22f9b65b7b6cfdc3086e0b5a1f3a14d9e7544a2 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -64,7 +64,7 @@
                                        reg = <1>;
 
                                        pmic_glink_con0_ss: endpoint {
-                                               remote-endpoint = <&mdss0_dp0_out>;
+                                               remote-endpoint = <&usb_0_qmpphy_out>;
                                        };
                                };
 
@@ -99,7 +99,7 @@
                                        reg = <1>;
 
                                        pmic_glink_con1_ss: endpoint {
-                                               remote-endpoint = <&mdss0_dp1_out>;
+                                               remote-endpoint = <&usb_1_qmpphy_out>;
                                        };
                                };
 
@@ -386,7 +386,7 @@
 
 &mdss0_dp0_out {
        data-lanes = <0 1>;
-       remote-endpoint = <&pmic_glink_con0_ss>;
+       remote-endpoint = <&usb_0_qmpphy_dp_in>;
 };
 
 &mdss0_dp1 {
@@ -395,7 +395,7 @@
 
 &mdss0_dp1_out {
        data-lanes = <0 1>;
-       remote-endpoint = <&pmic_glink_con1_ss>;
+       remote-endpoint = <&usb_1_qmpphy_dp_in>;
 };
 
 &mdss0_dp3 {
@@ -644,9 +644,19 @@
        vdda-phy-supply = <&vreg_l9d>;
        vdda-pll-supply = <&vreg_l4d>;
 
+       orientation-switch;
+
        status = "okay";
 };
 
+&usb_0_qmpphy_dp_in {
+       remote-endpoint = <&mdss0_dp0_out>;
+};
+
+&usb_0_qmpphy_out {
+       remote-endpoint = <&pmic_glink_con0_ss>;
+};
+
 &usb_0_role_switch {
        remote-endpoint = <&pmic_glink_con0_hs>;
 };
@@ -671,9 +681,19 @@
        vdda-phy-supply = <&vreg_l4b>;
        vdda-pll-supply = <&vreg_l3b>;
 
+       orientation-switch;
+
        status = "okay";
 };
 
+&usb_1_qmpphy_dp_in {
+       remote-endpoint = <&mdss0_dp1_out>;
+};
+
+&usb_1_qmpphy_out {
+       remote-endpoint = <&pmic_glink_con1_ss>;
+};
+
 &usb_1_role_switch {
        remote-endpoint = <&pmic_glink_con1_hs>;
 };

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 91a2d3ab3cc1c3bce540d982a786bf8a817e9f33..84ef3bd6d49a2df9fdf30331f02e49f78f3f4294 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2865,6 +2865,23 @@
                        #phy-cells = <1>;
 
                        status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+
+                                       usb_0_qmpphy_out: endpoint {};
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+
+                                       usb_0_qmpphy_dp_in: endpoint {};
+                               };
+                       };
                };
 
                usb_1_hsphy: phy@8902000 {
@@ -2901,6 +2918,23 @@
                        #phy-cells = <1>;
 
                        status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+
+                                       usb_1_qmpphy_out: endpoint {};
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+
+                                       usb_1_qmpphy_dp_in: endpoint {};
+                               };
+                       };
                };
 
                mdss1_dp0_phy: phy@8909a00 {