ath11k: don't call ath11k_pci_set_l1ss for WCN6855
authorBaochen Qiang <bqiang@codeaurora.org>
Mon, 31 May 2021 14:41:28 +0000 (17:41 +0300)
committerKalle Valo <kvalo@codeaurora.org>
Sat, 12 Jun 2021 10:31:05 +0000 (13:31 +0300)
For QCA6390, one PCI related clock drifts sometimes, and it makes
PCI link difficult to quit L1ss. Current implementation fixed this
by configuring some related regs using ath11k_pci_fix_l1ss.

WCN6855 does not have this clock drift problem, so no need to set
these regs.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1

Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Signed-off-by: Jouni Malinen <jouni@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20210511162214.29475-8-jouni@codeaurora.org
drivers/net/wireless/ath/ath11k/core.c
drivers/net/wireless/ath/ath11k/hw.h
drivers/net/wireless/ath/ath11k/pci.c

index fd8941905fdbcfa848eebe5f886e64ae2ab4b430..4a1051418f33a50b3320df59141bfd5b7c435f15 100644 (file)
@@ -70,6 +70,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
                .cold_boot_calib = true,
                .supports_suspend = false,
                .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
+               .fix_l1ss = true,
        },
        {
                .hw_rev = ATH11K_HW_IPQ6018_HW10,
@@ -110,6 +111,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
                .cold_boot_calib = true,
                .supports_suspend = false,
                .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
+               .fix_l1ss = true,
        },
        {
                .name = "qca6390 hw2.0",
@@ -149,6 +151,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
                .cold_boot_calib = false,
                .supports_suspend = true,
                .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
+               .fix_l1ss = true,
        },
        {
                .name = "qcn9074 hw1.0",
@@ -186,6 +189,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
                .cold_boot_calib = false,
                .supports_suspend = false,
                .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
+               .fix_l1ss = true,
        },
        {
                .name = "wcn6855 hw2.0",
@@ -225,6 +229,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
                .cold_boot_calib = false,
                .supports_suspend = true,
                .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
+               .fix_l1ss = false,
        },
 };
 
index be62f0c2e25e1d3d6b5bd0ff28566154133131a8..62f5978b30055a552f79a5024f82c4cd0c506e35 100644 (file)
@@ -162,6 +162,7 @@ struct ath11k_hw_params {
        bool cold_boot_calib;
        bool supports_suspend;
        u32 hal_desc_sz;
+       bool fix_l1ss;
 };
 
 struct ath11k_hw_ops {
index a4688b6beeb14be6b3ad7bb849fa388d30570652..f8f6b2090dad481ab28b0fa372836ec7ff61dea0 100644 (file)
@@ -434,7 +434,8 @@ static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
                ath11k_pci_enable_ltssm(ab);
                ath11k_pci_clear_all_intrs(ab);
                ath11k_pci_set_wlaon_pwr_ctrl(ab);
-               ath11k_pci_fix_l1ss(ab);
+               if (ab->hw_params.fix_l1ss)
+                       ath11k_pci_fix_l1ss(ab);
        }
 
        ath11k_mhi_clear_vector(ab);