arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]

Add asrc[0,1], esai0, spdif0, sai[4,5] and related lpcg node for
imx8 audio subsystem.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
index d8bbe53320bceba6a020dac1872142a76b07160f..897cbb7b6742205b296ee4d5e0986474ed9bfe82 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/imx8-clock.h>
 #include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/dma/fsl-edma.h>
 #include <dt-bindings/firmware/imx/rsrc.h>
 
 audio_ipg_clk: clock-audio-ipg {
@@ -119,6 +120,89 @@ audio_subsys: bus@59000000 {
        #size-cells = <1>;
        ranges = <0x59000000 0x0 0x59000000 0x1000000>;
 
+       asrc0: asrc@59000000 {
+               compatible = "fsl,imx8qm-asrc";
+               reg = <0x59000000 0x10000>;
+               interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
+                        <&asrc0_lpcg IMX_LPCG_CLK_0>,
+                        <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,
+                        <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,
+                        <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+                        <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>;
+               clock-names = "mem", "ipg",
+                             "asrck_0", "asrck_1", "asrck_2", "asrck_3",
+                             "asrck_4", "asrck_5", "asrck_6", "asrck_7",
+                             "asrck_8", "asrck_9", "asrck_a", "asrck_b",
+                             "asrck_c", "asrck_d", "asrck_e", "asrck_f",
+                             "spba";
+               dmas = <&edma0 0 0 0>,
+                      <&edma0 1 0 0>,
+                      <&edma0 2 0 0>,
+                      <&edma0 3 0 FSL_EDMA_RX>,
+                      <&edma0 4 0 FSL_EDMA_RX>,
+                      <&edma0 5 0 FSL_EDMA_RX>;
+               /* tx* is output channel of asrc, it is rx channel for eDMA */
+               dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
+               fsl,asrc-rate = <8000>;
+               fsl,asrc-width = <16>;
+               fsl,asrc-clk-map = <0>;
+               power-domains = <&pd IMX_SC_R_ASRC_0>;
+               status = "disabled";
+       };
+
+       esai0: esai@59010000 {
+               compatible = "fsl,imx8qm-esai";
+               reg = <0x59010000 0x10000>;
+               interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&esai0_lpcg IMX_LPCG_CLK_4>,
+                        <&esai0_lpcg IMX_LPCG_CLK_0>,
+                        <&esai0_lpcg IMX_LPCG_CLK_4>,
+                        <&clk_dummy>;
+               clock-names = "core", "extal", "fsys", "spba";
+               dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
+               dma-names = "rx", "tx";
+               power-domains = <&pd IMX_SC_R_ESAI_0>;
+               status = "disabled";
+       };
+
+       spdif0: spdif@59020000 {
+               compatible = "fsl,imx8qm-spdif";
+               reg = <0x59020000 0x10000>;
+               interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+                            <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+               clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */
+                        <&clk_dummy>,                  /* rxtx0 */
+                        <&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */
+                        <&clk_dummy>,                  /* rxtx2 */
+                        <&clk_dummy>,                  /* rxtx3 */
+                        <&clk_dummy>,                  /* rxtx4 */
+                        <&audio_ipg_clk>,              /* rxtx5 */
+                        <&clk_dummy>,                  /* rxtx6 */
+                        <&clk_dummy>,                  /* rxtx7 */
+                        <&clk_dummy>;                  /* spba */
+               clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
+                             "rxtx5", "rxtx6", "rxtx7", "spba";
+               dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
+                      <&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
+               dma-names = "rx", "tx";
+               power-domains = <&pd IMX_SC_R_SPDIF_0>;
+               status = "disabled";
+       };
+
        sai0: sai@59040000 {
                compatible = "fsl,imx8qm-sai";
                reg = <0x59040000 0x10000>;
@@ -239,6 +323,40 @@ audio_subsys: bus@59000000 {
                                <&pd IMX_SC_R_DMA_0_CH23>;
        };
 
+       asrc0_lpcg: clock-controller@59400000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x59400000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&audio_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_4>;
+               clock-output-names = "asrc0_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_ASRC_0>;
+       };
+
+       esai0_lpcg: clock-controller@59410000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x59410000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
+                        <&audio_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+               clock-output-names = "esai0_lpcg_extal_clk",
+                                    "esai0_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_ESAI_0>;
+       };
+
+       spdif0_lpcg: clock-controller@59420000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x59420000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
+                        <&audio_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+               clock-output-names = "spdif0_lpcg_tx_clk",
+                                    "spdif0_lpcg_gclkw";
+               power-domains = <&pd IMX_SC_R_SPDIF_0>;
+       };
+
        sai0_lpcg: clock-controller@59440000 {
                compatible = "fsl,imx8qxp-lpcg";
                reg = <0x59440000 0x10000>;
@@ -333,6 +451,101 @@ audio_subsys: bus@59000000 {
                status = "disabled";
        };
 
+       asrc1: asrc@59800000 {
+               compatible = "fsl,imx8qm-asrc";
+               reg = <0x59800000 0x10000>;
+               interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>,
+                        <&asrc1_lpcg IMX_LPCG_CLK_4>,
+                        <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+                        <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
+                        <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+                        <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>,
+                        <&clk_dummy>;
+               clock-names = "mem", "ipg",
+                             "asrck_0", "asrck_1", "asrck_2", "asrck_3",
+                             "asrck_4", "asrck_5", "asrck_6", "asrck_7",
+                             "asrck_8", "asrck_9", "asrck_a", "asrck_b",
+                             "asrck_c", "asrck_d", "asrck_e", "asrck_f",
+                             "spba";
+               dmas = <&edma1 0 0 0>,
+                      <&edma1 1 0 0>,
+                      <&edma1 2 0 0>,
+                      <&edma1 3 0 FSL_EDMA_RX>,
+                      <&edma1 4 0 FSL_EDMA_RX>,
+                      <&edma1 5 0 FSL_EDMA_RX>;
+               /* tx* is output channel of asrc, it is rx channel for eDMA */
+               dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
+               fsl,asrc-rate = <8000>;
+               fsl,asrc-width = <16>;
+               fsl,asrc-clk-map = <1>;
+               power-domains = <&pd IMX_SC_R_ASRC_1>;
+               status = "disabled";
+       };
+
+       sai4: sai@59820000 {
+               compatible = "fsl,imx8qm-sai";
+               reg = <0x59820000 0x10000>;
+               interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&sai4_lpcg IMX_LPCG_CLK_4>,
+                        <&clk_dummy>,
+                        <&sai4_lpcg IMX_LPCG_CLK_0>,
+                        <&clk_dummy>,
+                        <&clk_dummy>;
+               clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+               dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
+               dma-names = "rx", "tx";
+               power-domains = <&pd IMX_SC_R_SAI_4>;
+               status = "disabled";
+       };
+
+       sai5: sai@59830000 {
+               compatible = "fsl,imx8qm-sai";
+               reg = <0x59830000 0x10000>;
+               interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&sai5_lpcg IMX_LPCG_CLK_4>,
+                        <&clk_dummy>,
+                        <&sai5_lpcg IMX_LPCG_CLK_0>,
+                        <&clk_dummy>,
+                        <&clk_dummy>;
+               clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+               dmas = <&edma1 10 0 0>;
+               dma-names = "tx";
+               power-domains = <&pd IMX_SC_R_SAI_5>;
+               status = "disabled";
+       };
+
+       amix: amix@59840000 {
+               compatible = "fsl,imx8qm-audmix";
+               reg = <0x59840000 0x10000>;
+               clocks = <&amix_lpcg IMX_LPCG_CLK_0>;
+               clock-names = "ipg";
+               power-domains = <&pd IMX_SC_R_AMIX>;
+               dais = <&sai4>, <&sai5>;
+               status = "disabled";
+       };
+
+       mqs: mqs@59850000 {
+               compatible = "fsl,imx8qm-mqs";
+               reg = <0x59850000 0x10000>;
+               clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>;
+               clock-names = "mclk", "core";
+               power-domains = <&pd IMX_SC_R_MQS_0>;
+               status = "disabled";
+       };
+
        edma1: dma-controller@599f0000 {
                compatible = "fsl,imx8qm-edma";
                reg = <0x599f0000 0xc0000>;
@@ -481,4 +694,60 @@ audio_subsys: bus@59000000 {
                              "sai3_rx_bclk",
                              "sai4_rx_bclk";
        };
+
+       asrc1_lpcg: clock-controller@59c00000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x59c00000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&audio_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_4>;
+               clock-output-names = "asrc1_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_ASRC_1>;
+       };
+
+       sai4_lpcg: clock-controller@59c20000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x59c20000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
+                        <&audio_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+               clock-output-names = "sai4_lpcg_mclk",
+                                    "sai4_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_SAI_4>;
+       };
+
+       sai5_lpcg: clock-controller@59c30000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x59c30000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
+                        <&audio_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+               clock-output-names = "sai5_lpcg_mclk",
+                                    "sai5_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_SAI_5>;
+       };
+
+       amix_lpcg: clock-controller@59c40000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x59c40000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&audio_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>;
+               clock-output-names = "amix_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_AMIX>;
+       };
+
+       mqs0_lpcg: clock-controller@59c50000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x59c50000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
+                        <&audio_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+               clock-output-names = "mqs0_lpcg_mclk",
+                                    "mqs0_lpcg_ipg_clk";
+               power-domains = <&pd IMX_SC_R_MQS_0>;
+       };
 };