PCI: qcom: Allow ASPM L1 and substates for 2.7.0

Allow ASPM L1 and its substates.  By default this is disabled in the qcom
specific hardware.  Enable it explicitly only for controllers belonging to
2_7_0.

This does not affect any link capability registers; it will allow the link
transitions to L1 and its substates only if they are already supported.

Link: https://lore.kernel.org/r/1657886366-32685-1-git-send-email-quic_krichai@quicinc.com
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4530145162633d2bd5fe4fa60f4129fe2c2e2155..ccf6953fbc5d9c65bb1237e6706b1b06f1220d05 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -41,6 +41,9 @@
 #define L23_CLK_RMV_DIS                                BIT(2)
 #define L1_CLK_RMV_DIS                         BIT(1)
 
+#define PCIE20_PARF_PM_CTRL                    0x20
+#define REQ_NOT_ENTR_L1                                BIT(5)
+
 #define PCIE20_PARF_PHY_CTRL                   0x40
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK      GENMASK(20, 16)
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)                ((x) << 16)
@@ -1265,6 +1268,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
        val |= BIT(4);
        writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 
+       /* Enable L1 and L1SS */
+       val = readl(pcie->parf + PCIE20_PARF_PM_CTRL);
+       val &= ~REQ_NOT_ENTR_L1;
+       writel(val, pcie->parf + PCIE20_PARF_PM_CTRL);
+
        if (IS_ENABLED(CONFIG_PCI_MSI)) {
                val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
                val |= BIT(31);