PCI: qcom: Define some PARF params needed for ipq8064 SoC

Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
needed on some ipq8064 based device (Netgear R7800 for example). Without
this the system locks on kernel load.

Link: https://lore.kernel.org/r/20200615210608.21469-8-ansuelsmth@gmail.com
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: stable@vger.kernel.org # v4.5+

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8cb36cbcde46a9cb9c324892fea16ebd6964ba69..69c7b119e81a21196200433a6d86d9630da19ada 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -77,6 +77,18 @@
 #define DBI_RO_WR_EN                           1
 
 #define PERST_DELAY_US                         1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH                 0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)           ((x) << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)     ((x) << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)       ((x) << 0)
+
+#define PCIE20_PARF_PCS_SWING                  0x38
+#define PCS_SWING_TX_SWING_FULL(x)             ((x) << 8)
+#define PCS_SWING_TX_SWING_LOW(x)              ((x) << 0)
+
+#define PCIE20_PARF_CONFIG_BITS                0x50
+#define PHY_RX0_EQ(x)                          ((x) << 24)
 
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE     0x358
 #define SLV_ADDR_SPACE_SZ                      0x10000000
@@ -293,6 +305,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
        struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
        struct dw_pcie *pci = pcie->pci;
        struct device *dev = pci->dev;
+       struct device_node *node = dev->of_node;
        u32 val;
        int ret;
 
@@ -347,6 +360,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
        val &= ~BIT(0);
        writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
 
+       if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+               writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
+                              PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
+                              PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
+                      pcie->parf + PCIE20_PARF_PCS_DEEMPH);
+               writel(PCS_SWING_TX_SWING_FULL(120) |
+                              PCS_SWING_TX_SWING_LOW(120),
+                      pcie->parf + PCIE20_PARF_PCS_SWING);
+               writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
+       }
+
        /* enable external reference clock */
        val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
        val |= BIT(16);