MIPS: Loongson64: Bump ISA level to MIPSR2

Despite early sample of Loongson-3A1000, the whole Loongson64 family have
implemented all the features required by MIPS64 Release2. Thus we decide to
bump the ISA option to R2.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com
Cc: paul.burton@mips.com
Cc: linux-kernel@vger.kernel.org

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 75fca0cee9a22dc65b5cd77c7da2c714fda28912..08b6f3413c01b5efbdc5a8a328c6b69423a9f104 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1436,10 +1436,14 @@ config CPU_LOONGSON64
        bool "Loongson 64-bit CPU"
        depends on SYS_HAS_CPU_LOONGSON64
        select ARCH_HAS_PHYS_TO_DMA
+       select CPU_MIPSR2
+       select CPU_HAS_PREFETCH
        select CPU_SUPPORTS_64BIT_KERNEL
        select CPU_SUPPORTS_HIGHMEM
        select CPU_SUPPORTS_HUGEPAGES
        select CPU_SUPPORTS_MSA
+       select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
+       select CPU_MIPSR2_IRQ_VI
        select WEAK_ORDERING
        select WEAK_REORDERING_BEYOND_LLSC
        select MIPS_ASID_BITS_VARIABLE
@@ -1457,8 +1461,6 @@ config CPU_LOONGSON64
 config LOONGSON3_ENHANCEMENT
        bool "New Loongson-3 CPU Enhancements"
        default n
-       select CPU_MIPSR2
-       select CPU_HAS_PREFETCH
        depends on CPU_LOONGSON64
        help
          New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index a4f48b0f55419961b0f756a71ece4ae460a156e7..a0b92205f93393ce1392004eb1626924f538f9bd 100644 (file)
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -23,7 +23,7 @@
  * TLB hazards
  */
 #if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
-       !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)
+       !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
 
 /*
  * MIPSR2 defines ehb for hazard avoidance
@@ -158,7 +158,7 @@ do {                                                                        \
 } while (0)
 
 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-       defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
+       defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
        defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
 
 /*