arm/index
arm64/index
ia64/index
- ../loongarch/index
+ loongarch/index
m68k/index
../mips/index
nios2/index
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+=======================
+Booting Linux/LoongArch
+=======================
+
+:Author: Yanteng Si <siyanteng@loongson.cn>
+:Date: 18 Nov 2022
+
+Information passed from BootLoader to kernel
+============================================
+
+LoongArch supports ACPI and FDT. The information that needs to be passed
+to the kernel includes the memmap, the initrd, the command line, optionally
+the ACPI/FDT tables, and so on.
+
+The kernel is passed the following arguments on `kernel_entry` :
+
+ - a0 = efi_boot: `efi_boot` is a flag indicating whether
+ this boot environment is fully UEFI-compliant.
+
+ - a1 = cmdline: `cmdline` is a pointer to the kernel command line.
+
+ - a2 = systemtable: `systemtable` points to the EFI system table.
+ All pointers involved at this stage are in physical addresses.
+
+Header of Linux/LoongArch kernel images
+=======================================
+
+Linux/LoongArch kernel images are EFI images. Being PE files, they have
+a 64-byte header structured like::
+
+ u32 MZ_MAGIC /* "MZ", MS-DOS header */
+ u32 res0 = 0 /* Reserved */
+ u64 kernel_entry /* Kernel entry point */
+ u64 _end - _text /* Kernel image effective size */
+ u64 load_offset /* Kernel image load offset from start of RAM */
+ u64 res1 = 0 /* Reserved */
+ u64 res2 = 0 /* Reserved */
+ u64 res3 = 0 /* Reserved */
+ u32 LINUX_PE_MAGIC /* Magic number */
+ u32 pe_header - _head /* Offset to the PE header */
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+.. kernel-feat:: $srctree/Documentation/features loongarch
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+======================
+LoongArch Architecture
+======================
+
+.. toctree::
+ :maxdepth: 2
+ :numbered:
+
+ introduction
+ booting
+ irq-chip-model
+
+ features
+
+.. only:: subproject and html
+
+ Indices
+ =======
+
+ * :ref:`genindex`
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+=========================
+Introduction to LoongArch
+=========================
+
+LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
+currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
+version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
+(PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV0
+while applications run at PLV3. This document introduces the registers, basic
+instruction set, virtual memory and some other topics of LoongArch.
+
+Registers
+=========
+
+LoongArch registers include general purpose registers (GPRs), floating point
+registers (FPRs), vector registers (VRs) and control status registers (CSRs)
+used in privileged mode (PLV0).
+
+GPRs
+----
+
+LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
+and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
+are not architecturally special. (Except ``$r1``, which is hard-wired as the
+link register of the BL instruction.)
+
+The kernel uses a variant of the LoongArch register convention, as described in
+the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
+
+================= =============== =================== ============
+Name Alias Usage Preserved
+ across calls
+================= =============== =================== ============
+``$r0`` ``$zero`` Constant zero Unused
+``$r1`` ``$ra`` Return address No
+``$r2`` ``$tp`` TLS/Thread pointer Unused
+``$r3`` ``$sp`` Stack pointer Yes
+``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
+``$r4``-``$r5`` ``$v0``-``$v1`` Return value No
+``$r12``-``$r20`` ``$t0``-``$t8`` Temp registers No
+``$r21`` ``$u0`` Percpu base address Unused
+``$r22`` ``$fp`` Frame pointer Yes
+``$r23``-``$r31`` ``$s0``-``$s8`` Static registers Yes
+================= =============== =================== ============
+
+.. Note::
+ The register ``$r21`` is reserved in the ELF psABI, but used by the Linux
+ kernel for storing the percpu base address. It normally has no ABI name,
+ but is called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1``
+ in some old code,however they are deprecated aliases of ``$a0`` and ``$a1``
+ respectively.
+
+FPRs
+----
+
+LoongArch has 32 FPRs ( ``$f0`` ~ ``$f31`` ) when FPU is present. Each one is
+64-bit wide on the LA64 cores.
+
+The floating-point register convention is the same as described in the
+LoongArch ELF psABI spec:
+
+================= ================== =================== ============
+Name Alias Usage Preserved
+ across calls
+================= ================== =================== ============
+``$f0``-``$f7`` ``$fa0``-``$fa7`` Argument registers No
+``$f0``-``$f1`` ``$fv0``-``$fv1`` Return value No
+``$f8``-``$f23`` ``$ft0``-``$ft15`` Temp registers No
+``$f24``-``$f31`` ``$fs0``-``$fs7`` Static registers Yes
+================= ================== =================== ============
+
+.. Note::
+ You may see ``$fv0`` or ``$fv1`` in some old code, however they are
+ deprecated aliases of ``$fa0`` and ``$fa1`` respectively.
+
+VRs
+----
+
+There are currently 2 vector extensions to LoongArch:
+
+- LSX (Loongson SIMD eXtension) with 128-bit vectors,
+- LASX (Loongson Advanced SIMD eXtension) with 256-bit vectors.
+
+LSX brings ``$v0`` ~ ``$v31`` while LASX brings ``$x0`` ~ ``$x31`` as the vector
+registers.
+
+The VRs overlap with FPRs: for example, on a core implementing LSX and LASX,
+the lower 128 bits of ``$x0`` is shared with ``$v0``, and the lower 64 bits of
+``$v0`` is shared with ``$f0``; same with all other VRs.
+
+CSRs
+----
+
+CSRs can only be accessed from privileged mode (PLV0):
+
+================= ===================================== ==============
+Address Full Name Abbrev Name
+================= ===================================== ==============
+0x0 Current Mode Information CRMD
+0x1 Pre-exception Mode Information PRMD
+0x2 Extension Unit Enable EUEN
+0x3 Miscellaneous Control MISC
+0x4 Exception Configuration ECFG
+0x5 Exception Status ESTAT
+0x6 Exception Return Address ERA
+0x7 Bad (Faulting) Virtual Address BADV
+0x8 Bad (Faulting) Instruction Word BADI
+0xC Exception Entrypoint Address EENTRY
+0x10 TLB Index TLBIDX
+0x11 TLB Entry High-order Bits TLBEHI
+0x12 TLB Entry Low-order Bits 0 TLBELO0
+0x13 TLB Entry Low-order Bits 1 TLBELO1
+0x18 Address Space Identifier ASID
+0x19 Page Global Directory Address for PGDL
+ Lower-half Address Space
+0x1A Page Global Directory Address for PGDH
+ Higher-half Address Space
+0x1B Page Global Directory Address PGD
+0x1C Page Walk Control for Lower- PWCL
+ half Address Space
+0x1D Page Walk Control for Higher- PWCH
+ half Address Space
+0x1E STLB Page Size STLBPS
+0x1F Reduced Virtual Address Configuration RVACFG
+0x20 CPU Identifier CPUID
+0x21 Privileged Resource Configuration 1 PRCFG1
+0x22 Privileged Resource Configuration 2 PRCFG2
+0x23 Privileged Resource Configuration 3 PRCFG3
+0x30+n (0≤n≤15) Saved Data register SAVEn
+0x40 Timer Identifier TID
+0x41 Timer Configuration TCFG
+0x42 Timer Value TVAL
+0x43 Compensation of Timer Count CNTC
+0x44 Timer Interrupt Clearing TICLR
+0x60 LLBit Control LLBCTL
+0x80 Implementation-specific Control 1 IMPCTL1
+0x81 Implementation-specific Control 2 IMPCTL2
+0x88 TLB Refill Exception Entrypoint TLBRENTRY
+ Address
+0x89 TLB Refill Exception BAD (Faulting) TLBRBADV
+ Virtual Address
+0x8A TLB Refill Exception Return Address TLBRERA
+0x8B TLB Refill Exception Saved Data TLBRSAVE
+ Register
+0x8C TLB Refill Exception Entry Low-order TLBRELO0
+ Bits 0
+0x8D TLB Refill Exception Entry Low-order TLBRELO1
+ Bits 1
+0x8E TLB Refill Exception Entry High-order TLBEHI
+ Bits
+0x8F TLB Refill Exception Pre-exception TLBRPRMD
+ Mode Information
+0x90 Machine Error Control MERRCTL
+0x91 Machine Error Information 1 MERRINFO1
+0x92 Machine Error Information 2 MERRINFO2
+0x93 Machine Error Exception Entrypoint MERRENTRY
+ Address
+0x94 Machine Error Exception Return MERRERA
+ Address
+0x95 Machine Error Exception Saved Data MERRSAVE
+ Register
+0x98 Cache TAGs CTAG
+0x180+n (0≤n≤3) Direct Mapping Configuration Window n DMWn
+0x200+2n (0≤n≤31) Performance Monitor Configuration n PMCFGn
+0x201+2n (0≤n≤31) Performance Monitor Overall Counter n PMCNTn
+0x300 Memory Load/Store WatchPoint MWPC
+ Overall Control
+0x301 Memory Load/Store WatchPoint MWPS
+ Overall Status
+0x310+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG1
+ Configuration 1
+0x311+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG2
+ Configuration 2
+0x312+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG3
+ Configuration 3
+0x313+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG4
+ Configuration 4
+0x380 Instruction Fetch WatchPoint FWPC
+ Overall Control
+0x381 Instruction Fetch WatchPoint FWPS
+ Overall Status
+0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1
+ Configuration 1
+0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2
+ Configuration 2
+0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3
+ Configuration 3
+0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4
+ Configuration 4
+0x500 Debug Register DBG
+0x501 Debug Exception Return Address DERA
+0x502 Debug Exception Saved Data Register DSAVE
+================= ===================================== ==============
+
+ERA, TLBRERA, MERRERA and DERA are sometimes also known as EPC, TLBREPC, MERREPC
+and DEPC respectively.
+
+Basic Instruction Set
+=====================
+
+Instruction formats
+-------------------
+
+LoongArch instructions are 32 bits wide, belonging to 9 basic instruction
+formats (and variants of them):
+
+=========== ==========================
+Format name Composition
+=========== ==========================
+2R Opcode + Rj + Rd
+3R Opcode + Rk + Rj + Rd
+4R Opcode + Ra + Rk + Rj + Rd
+2RI8 Opcode + I8 + Rj + Rd
+2RI12 Opcode + I12 + Rj + Rd
+2RI14 Opcode + I14 + Rj + Rd
+2RI16 Opcode + I16 + Rj + Rd
+1RI21 Opcode + I21L + Rj + I21H
+I26 Opcode + I26L + I26H
+=========== ==========================
+
+Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for
+"additional") are the source register operands. I8/I12/I14/I16/I21/I26 are
+immediate operands of respective width. The longer I21 and I26 are stored
+in separate higher and lower parts in the instruction word, denoted by the "L"
+and "H" suffixes.
+
+List of Instructions
+--------------------
+
+For brevity, only instruction names (mnemonics) are listed here; please see the
+:ref:`References <loongarch-references>` for details.
+
+
+1. Arithmetic Instructions::
+
+ ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
+ SLT SLTU SLTI SLTUI
+ AND OR NOR XOR ANDN ORN ANDI ORI XORI
+ MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
+ MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
+ PCADDI PCADDU12I PCADDU18I
+ LU12I.W LU32I.D LU52I.D ADDU16I.D
+
+2. Bit-shift Instructions::
+
+ SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
+ SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
+
+3. Bit-manipulation Instructions::
+
+ EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
+ BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
+ REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
+ MASKEQZ MASKNEZ
+
+4. Branch Instructions::
+
+ BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
+
+5. Load/Store Instructions::
+
+ LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
+ LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
+ LDPTR.W LDPTR.D STPTR.W STPTR.D
+ PRELD PRELDX
+
+6. Atomic Operation Instructions::
+
+ LL.W SC.W LL.D SC.D
+ AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
+ AMMAX.W AMMAX.D AMMIN.W AMMIN.D
+
+7. Barrier Instructions::
+
+ IBAR DBAR
+
+8. Special Instructions::
+
+ SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D
+ ASRTLE.D ASRTGT.D
+
+9. Privileged Instructions::
+
+ CSRRD CSRWR CSRXCHG
+ IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
+ CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
+
+Virtual Memory
+==============
+
+LoongArch supports direct-mapped virtual memory and page-mapped virtual memory.
+
+Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple
+relationship between virtual address (VA) and physical address (PA)::
+
+ VA = PA + FixedOffset
+
+Page-mapped virtual memory has arbitrary relationship between VA and PA, which
+is recorded in TLB and page tables. LoongArch's TLB includes a fully-associative
+MTLB (Multiple Page Size TLB) and set-associative STLB (Single Page Size TLB).
+
+By default, the whole virtual address space of LA32 is configured like this:
+
+============ =========================== =============================
+Name Address Range Attributes
+============ =========================== =============================
+``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` Page-mapped, Cached, PLV0~3
+``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` Direct-mapped, Uncached, PLV0
+``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` Direct-mapped, Cached, PLV0
+``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` Page-mapped, Cached, PLV0
+============ =========================== =============================
+
+User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and
+KPRANGE1, PA is equal to VA with bit30~31 cleared. For example, the uncached
+direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped
+VA of 0x00001000 is 0xA0001000.
+
+By default, the whole virtual address space of LA64 is configured like this:
+
+============ ====================== ======================================
+Name Address Range Attributes
+============ ====================== ======================================
+``XUVRANGE`` ``0x0000000000000000 - Page-mapped, Cached, PLV0~3
+ 0x3FFFFFFFFFFFFFFF``
+``XSPRANGE`` ``0x4000000000000000 - Direct-mapped, Cached / Uncached, PLV0
+ 0x7FFFFFFFFFFFFFFF``
+``XKPRANGE`` ``0x8000000000000000 - Direct-mapped, Cached / Uncached, PLV0
+ 0xBFFFFFFFFFFFFFFF``
+``XKVRANGE`` ``0xC000000000000000 - Page-mapped, Cached, PLV0
+ 0xFFFFFFFFFFFFFFFF``
+============ ====================== ======================================
+
+User mode (PLV3) can only access XUVRANGE. For direct-mapped XSPRANGE and
+XKPRANGE, PA is equal to VA with bits 60~63 cleared, and the cache attribute
+is configured by bits 60~61 in VA: 0 is for strongly-ordered uncached, 1 is
+for coherent cached, and 2 is for weakly-ordered uncached.
+
+Currently we only use XKPRANGE for direct mapping and XSPRANGE is reserved.
+
+To put this in action: the strongly-ordered uncached direct-mapped VA (in
+XKPRANGE) of 0x00000000_00001000 is 0x80000000_00001000, the coherent cached
+direct-mapped VA (in XKPRANGE) of 0x00000000_00001000 is 0x90000000_00001000,
+and the weakly-ordered uncached direct-mapped VA (in XKPRANGE) of 0x00000000
+_00001000 is 0xA0000000_00001000.
+
+Relationship of Loongson and LoongArch
+======================================
+
+LoongArch is a RISC ISA which is different from any other existing ones, while
+Loongson is a family of processors. Loongson includes 3 series: Loongson-1 is
+the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series,
+and Loongson-3 is the high-end 64-bit processor series. Old Loongson is based on
+MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example:
+Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson-
+3A5000 (and future revisions) are all based on LoongArch.
+
+.. _loongarch-references:
+
+References
+==========
+
+Official web site of Loongson Technology Corp. Ltd.:
+
+ http://www.loongson.cn/
+
+Developer web site of Loongson and LoongArch (Software and Documentation):
+
+ http://www.loongnix.cn/
+
+ https://github.com/loongson/
+
+ https://loongson.github.io/LoongArch-Documentation/
+
+Documentation of LoongArch ISA:
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-CN.pdf (in Chinese)
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-EN.pdf (in English)
+
+Documentation of LoongArch ELF psABI:
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-CN.pdf (in Chinese)
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-EN.pdf (in English)
+
+Linux kernel repository of Loongson and LoongArch:
+
+ https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+=======================================
+IRQ chip model (hierarchy) of LoongArch
+=======================================
+
+Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
+with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
+Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
+I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
+PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
+in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
+
+CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
+controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
+in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
+and there are two models of hierarchy (legacy model and extended model).
+
+Legacy IRQ model
+================
+
+In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
+to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
+interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
+to LIOINTC, and then CPUINTC::
+
+ +-----+ +---------+ +-------+
+ | IPI | --> | CPUINTC | <-- | Timer |
+ +-----+ +---------+ +-------+
+ ^
+ |
+ +---------+ +-------+
+ | LIOINTC | <-- | UARTs |
+ +---------+ +-------+
+ ^
+ |
+ +-----------+
+ | HTVECINTC |
+ +-----------+
+ ^ ^
+ | |
+ +---------+ +---------+
+ | PCH-PIC | | PCH-MSI |
+ +---------+ +---------+
+ ^ ^ ^
+ | | |
+ +---------+ +---------+ +---------+
+ | PCH-LPC | | Devices | | Devices |
+ +---------+ +---------+ +---------+
+ ^
+ |
+ +---------+
+ | Devices |
+ +---------+
+
+Extended IRQ model
+==================
+
+In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
+to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
+interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
+to CPUINTC directly::
+
+ +-----+ +---------+ +-------+
+ | IPI | --> | CPUINTC | <-- | Timer |
+ +-----+ +---------+ +-------+
+ ^ ^
+ | |
+ +---------+ +---------+ +-------+
+ | EIOINTC | | LIOINTC | <-- | UARTs |
+ +---------+ +---------+ +-------+
+ ^ ^
+ | |
+ +---------+ +---------+
+ | PCH-PIC | | PCH-MSI |
+ +---------+ +---------+
+ ^ ^ ^
+ | | |
+ +---------+ +---------+ +---------+
+ | PCH-LPC | | Devices | | Devices |
+ +---------+ +---------+ +---------+
+ ^
+ |
+ +---------+
+ | Devices |
+ +---------+
+
+ACPI-related definitions
+========================
+
+CPUINTC::
+
+ ACPI_MADT_TYPE_CORE_PIC;
+ struct acpi_madt_core_pic;
+ enum acpi_madt_core_pic_version;
+
+LIOINTC::
+
+ ACPI_MADT_TYPE_LIO_PIC;
+ struct acpi_madt_lio_pic;
+ enum acpi_madt_lio_pic_version;
+
+EIOINTC::
+
+ ACPI_MADT_TYPE_EIO_PIC;
+ struct acpi_madt_eio_pic;
+ enum acpi_madt_eio_pic_version;
+
+HTVECINTC::
+
+ ACPI_MADT_TYPE_HT_PIC;
+ struct acpi_madt_ht_pic;
+ enum acpi_madt_ht_pic_version;
+
+PCH-PIC::
+
+ ACPI_MADT_TYPE_BIO_PIC;
+ struct acpi_madt_bio_pic;
+ enum acpi_madt_bio_pic_version;
+
+PCH-MSI::
+
+ ACPI_MADT_TYPE_MSI_PIC;
+ struct acpi_madt_msi_pic;
+ enum acpi_madt_msi_pic_version;
+
+PCH-LPC::
+
+ ACPI_MADT_TYPE_LPC_PIC;
+ struct acpi_madt_lpc_pic;
+ enum acpi_madt_lpc_pic_version;
+
+References
+==========
+
+Documentation of Loongson-3A5000:
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)
+
+Documentation of Loongson's LS7A chipset:
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
+
+.. Note::
+ - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
+ in Section 7.4 of "LoongArch Reference Manual, Vol 1";
+ - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
+ "Loongson 3A5000 Processor Reference Manual";
+ - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
+ "Loongson 3A5000 Processor Reference Manual";
+ - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
+ "Loongson 3A5000 Processor Reference Manual";
+ - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
+ "Loongson 7A1000 Bridge User Manual";
+ - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
+ "Loongson 7A1000 Bridge User Manual".
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-=======================
-Booting Linux/LoongArch
-=======================
-
-:Author: Yanteng Si <siyanteng@loongson.cn>
-:Date: 18 Nov 2022
-
-Information passed from BootLoader to kernel
-============================================
-
-LoongArch supports ACPI and FDT. The information that needs to be passed
-to the kernel includes the memmap, the initrd, the command line, optionally
-the ACPI/FDT tables, and so on.
-
-The kernel is passed the following arguments on `kernel_entry` :
-
- - a0 = efi_boot: `efi_boot` is a flag indicating whether
- this boot environment is fully UEFI-compliant.
-
- - a1 = cmdline: `cmdline` is a pointer to the kernel command line.
-
- - a2 = systemtable: `systemtable` points to the EFI system table.
- All pointers involved at this stage are in physical addresses.
-
-Header of Linux/LoongArch kernel images
-=======================================
-
-Linux/LoongArch kernel images are EFI images. Being PE files, they have
-a 64-byte header structured like::
-
- u32 MZ_MAGIC /* "MZ", MS-DOS header */
- u32 res0 = 0 /* Reserved */
- u64 kernel_entry /* Kernel entry point */
- u64 _end - _text /* Kernel image effective size */
- u64 load_offset /* Kernel image load offset from start of RAM */
- u64 res1 = 0 /* Reserved */
- u64 res2 = 0 /* Reserved */
- u64 res3 = 0 /* Reserved */
- u32 LINUX_PE_MAGIC /* Magic number */
- u32 pe_header - _head /* Offset to the PE header */
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-.. kernel-feat:: $srctree/Documentation/features loongarch
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-======================
-LoongArch Architecture
-======================
-
-.. toctree::
- :maxdepth: 2
- :numbered:
-
- introduction
- booting
- irq-chip-model
-
- features
-
-.. only:: subproject and html
-
- Indices
- =======
-
- * :ref:`genindex`
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-=========================
-Introduction to LoongArch
-=========================
-
-LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
-currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
-version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
-(PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV0
-while applications run at PLV3. This document introduces the registers, basic
-instruction set, virtual memory and some other topics of LoongArch.
-
-Registers
-=========
-
-LoongArch registers include general purpose registers (GPRs), floating point
-registers (FPRs), vector registers (VRs) and control status registers (CSRs)
-used in privileged mode (PLV0).
-
-GPRs
-----
-
-LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
-and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
-are not architecturally special. (Except ``$r1``, which is hard-wired as the
-link register of the BL instruction.)
-
-The kernel uses a variant of the LoongArch register convention, as described in
-the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
-
-================= =============== =================== ============
-Name Alias Usage Preserved
- across calls
-================= =============== =================== ============
-``$r0`` ``$zero`` Constant zero Unused
-``$r1`` ``$ra`` Return address No
-``$r2`` ``$tp`` TLS/Thread pointer Unused
-``$r3`` ``$sp`` Stack pointer Yes
-``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
-``$r4``-``$r5`` ``$v0``-``$v1`` Return value No
-``$r12``-``$r20`` ``$t0``-``$t8`` Temp registers No
-``$r21`` ``$u0`` Percpu base address Unused
-``$r22`` ``$fp`` Frame pointer Yes
-``$r23``-``$r31`` ``$s0``-``$s8`` Static registers Yes
-================= =============== =================== ============
-
-.. Note::
- The register ``$r21`` is reserved in the ELF psABI, but used by the Linux
- kernel for storing the percpu base address. It normally has no ABI name,
- but is called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1``
- in some old code,however they are deprecated aliases of ``$a0`` and ``$a1``
- respectively.
-
-FPRs
-----
-
-LoongArch has 32 FPRs ( ``$f0`` ~ ``$f31`` ) when FPU is present. Each one is
-64-bit wide on the LA64 cores.
-
-The floating-point register convention is the same as described in the
-LoongArch ELF psABI spec:
-
-================= ================== =================== ============
-Name Alias Usage Preserved
- across calls
-================= ================== =================== ============
-``$f0``-``$f7`` ``$fa0``-``$fa7`` Argument registers No
-``$f0``-``$f1`` ``$fv0``-``$fv1`` Return value No
-``$f8``-``$f23`` ``$ft0``-``$ft15`` Temp registers No
-``$f24``-``$f31`` ``$fs0``-``$fs7`` Static registers Yes
-================= ================== =================== ============
-
-.. Note::
- You may see ``$fv0`` or ``$fv1`` in some old code, however they are
- deprecated aliases of ``$fa0`` and ``$fa1`` respectively.
-
-VRs
-----
-
-There are currently 2 vector extensions to LoongArch:
-
-- LSX (Loongson SIMD eXtension) with 128-bit vectors,
-- LASX (Loongson Advanced SIMD eXtension) with 256-bit vectors.
-
-LSX brings ``$v0`` ~ ``$v31`` while LASX brings ``$x0`` ~ ``$x31`` as the vector
-registers.
-
-The VRs overlap with FPRs: for example, on a core implementing LSX and LASX,
-the lower 128 bits of ``$x0`` is shared with ``$v0``, and the lower 64 bits of
-``$v0`` is shared with ``$f0``; same with all other VRs.
-
-CSRs
-----
-
-CSRs can only be accessed from privileged mode (PLV0):
-
-================= ===================================== ==============
-Address Full Name Abbrev Name
-================= ===================================== ==============
-0x0 Current Mode Information CRMD
-0x1 Pre-exception Mode Information PRMD
-0x2 Extension Unit Enable EUEN
-0x3 Miscellaneous Control MISC
-0x4 Exception Configuration ECFG
-0x5 Exception Status ESTAT
-0x6 Exception Return Address ERA
-0x7 Bad (Faulting) Virtual Address BADV
-0x8 Bad (Faulting) Instruction Word BADI
-0xC Exception Entrypoint Address EENTRY
-0x10 TLB Index TLBIDX
-0x11 TLB Entry High-order Bits TLBEHI
-0x12 TLB Entry Low-order Bits 0 TLBELO0
-0x13 TLB Entry Low-order Bits 1 TLBELO1
-0x18 Address Space Identifier ASID
-0x19 Page Global Directory Address for PGDL
- Lower-half Address Space
-0x1A Page Global Directory Address for PGDH
- Higher-half Address Space
-0x1B Page Global Directory Address PGD
-0x1C Page Walk Control for Lower- PWCL
- half Address Space
-0x1D Page Walk Control for Higher- PWCH
- half Address Space
-0x1E STLB Page Size STLBPS
-0x1F Reduced Virtual Address Configuration RVACFG
-0x20 CPU Identifier CPUID
-0x21 Privileged Resource Configuration 1 PRCFG1
-0x22 Privileged Resource Configuration 2 PRCFG2
-0x23 Privileged Resource Configuration 3 PRCFG3
-0x30+n (0≤n≤15) Saved Data register SAVEn
-0x40 Timer Identifier TID
-0x41 Timer Configuration TCFG
-0x42 Timer Value TVAL
-0x43 Compensation of Timer Count CNTC
-0x44 Timer Interrupt Clearing TICLR
-0x60 LLBit Control LLBCTL
-0x80 Implementation-specific Control 1 IMPCTL1
-0x81 Implementation-specific Control 2 IMPCTL2
-0x88 TLB Refill Exception Entrypoint TLBRENTRY
- Address
-0x89 TLB Refill Exception BAD (Faulting) TLBRBADV
- Virtual Address
-0x8A TLB Refill Exception Return Address TLBRERA
-0x8B TLB Refill Exception Saved Data TLBRSAVE
- Register
-0x8C TLB Refill Exception Entry Low-order TLBRELO0
- Bits 0
-0x8D TLB Refill Exception Entry Low-order TLBRELO1
- Bits 1
-0x8E TLB Refill Exception Entry High-order TLBEHI
- Bits
-0x8F TLB Refill Exception Pre-exception TLBRPRMD
- Mode Information
-0x90 Machine Error Control MERRCTL
-0x91 Machine Error Information 1 MERRINFO1
-0x92 Machine Error Information 2 MERRINFO2
-0x93 Machine Error Exception Entrypoint MERRENTRY
- Address
-0x94 Machine Error Exception Return MERRERA
- Address
-0x95 Machine Error Exception Saved Data MERRSAVE
- Register
-0x98 Cache TAGs CTAG
-0x180+n (0≤n≤3) Direct Mapping Configuration Window n DMWn
-0x200+2n (0≤n≤31) Performance Monitor Configuration n PMCFGn
-0x201+2n (0≤n≤31) Performance Monitor Overall Counter n PMCNTn
-0x300 Memory Load/Store WatchPoint MWPC
- Overall Control
-0x301 Memory Load/Store WatchPoint MWPS
- Overall Status
-0x310+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG1
- Configuration 1
-0x311+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG2
- Configuration 2
-0x312+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG3
- Configuration 3
-0x313+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG4
- Configuration 4
-0x380 Instruction Fetch WatchPoint FWPC
- Overall Control
-0x381 Instruction Fetch WatchPoint FWPS
- Overall Status
-0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1
- Configuration 1
-0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2
- Configuration 2
-0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3
- Configuration 3
-0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4
- Configuration 4
-0x500 Debug Register DBG
-0x501 Debug Exception Return Address DERA
-0x502 Debug Exception Saved Data Register DSAVE
-================= ===================================== ==============
-
-ERA, TLBRERA, MERRERA and DERA are sometimes also known as EPC, TLBREPC, MERREPC
-and DEPC respectively.
-
-Basic Instruction Set
-=====================
-
-Instruction formats
--------------------
-
-LoongArch instructions are 32 bits wide, belonging to 9 basic instruction
-formats (and variants of them):
-
-=========== ==========================
-Format name Composition
-=========== ==========================
-2R Opcode + Rj + Rd
-3R Opcode + Rk + Rj + Rd
-4R Opcode + Ra + Rk + Rj + Rd
-2RI8 Opcode + I8 + Rj + Rd
-2RI12 Opcode + I12 + Rj + Rd
-2RI14 Opcode + I14 + Rj + Rd
-2RI16 Opcode + I16 + Rj + Rd
-1RI21 Opcode + I21L + Rj + I21H
-I26 Opcode + I26L + I26H
-=========== ==========================
-
-Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for
-"additional") are the source register operands. I8/I12/I14/I16/I21/I26 are
-immediate operands of respective width. The longer I21 and I26 are stored
-in separate higher and lower parts in the instruction word, denoted by the "L"
-and "H" suffixes.
-
-List of Instructions
---------------------
-
-For brevity, only instruction names (mnemonics) are listed here; please see the
-:ref:`References <loongarch-references>` for details.
-
-
-1. Arithmetic Instructions::
-
- ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
- SLT SLTU SLTI SLTUI
- AND OR NOR XOR ANDN ORN ANDI ORI XORI
- MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
- MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
- PCADDI PCADDU12I PCADDU18I
- LU12I.W LU32I.D LU52I.D ADDU16I.D
-
-2. Bit-shift Instructions::
-
- SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
- SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
-
-3. Bit-manipulation Instructions::
-
- EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
- BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
- REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
- MASKEQZ MASKNEZ
-
-4. Branch Instructions::
-
- BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
-
-5. Load/Store Instructions::
-
- LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
- LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
- LDPTR.W LDPTR.D STPTR.W STPTR.D
- PRELD PRELDX
-
-6. Atomic Operation Instructions::
-
- LL.W SC.W LL.D SC.D
- AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
- AMMAX.W AMMAX.D AMMIN.W AMMIN.D
-
-7. Barrier Instructions::
-
- IBAR DBAR
-
-8. Special Instructions::
-
- SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D
- ASRTLE.D ASRTGT.D
-
-9. Privileged Instructions::
-
- CSRRD CSRWR CSRXCHG
- IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
- CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
-
-Virtual Memory
-==============
-
-LoongArch supports direct-mapped virtual memory and page-mapped virtual memory.
-
-Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple
-relationship between virtual address (VA) and physical address (PA)::
-
- VA = PA + FixedOffset
-
-Page-mapped virtual memory has arbitrary relationship between VA and PA, which
-is recorded in TLB and page tables. LoongArch's TLB includes a fully-associative
-MTLB (Multiple Page Size TLB) and set-associative STLB (Single Page Size TLB).
-
-By default, the whole virtual address space of LA32 is configured like this:
-
-============ =========================== =============================
-Name Address Range Attributes
-============ =========================== =============================
-``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` Page-mapped, Cached, PLV0~3
-``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` Direct-mapped, Uncached, PLV0
-``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` Direct-mapped, Cached, PLV0
-``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` Page-mapped, Cached, PLV0
-============ =========================== =============================
-
-User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and
-KPRANGE1, PA is equal to VA with bit30~31 cleared. For example, the uncached
-direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped
-VA of 0x00001000 is 0xA0001000.
-
-By default, the whole virtual address space of LA64 is configured like this:
-
-============ ====================== ======================================
-Name Address Range Attributes
-============ ====================== ======================================
-``XUVRANGE`` ``0x0000000000000000 - Page-mapped, Cached, PLV0~3
- 0x3FFFFFFFFFFFFFFF``
-``XSPRANGE`` ``0x4000000000000000 - Direct-mapped, Cached / Uncached, PLV0
- 0x7FFFFFFFFFFFFFFF``
-``XKPRANGE`` ``0x8000000000000000 - Direct-mapped, Cached / Uncached, PLV0
- 0xBFFFFFFFFFFFFFFF``
-``XKVRANGE`` ``0xC000000000000000 - Page-mapped, Cached, PLV0
- 0xFFFFFFFFFFFFFFFF``
-============ ====================== ======================================
-
-User mode (PLV3) can only access XUVRANGE. For direct-mapped XSPRANGE and
-XKPRANGE, PA is equal to VA with bits 60~63 cleared, and the cache attribute
-is configured by bits 60~61 in VA: 0 is for strongly-ordered uncached, 1 is
-for coherent cached, and 2 is for weakly-ordered uncached.
-
-Currently we only use XKPRANGE for direct mapping and XSPRANGE is reserved.
-
-To put this in action: the strongly-ordered uncached direct-mapped VA (in
-XKPRANGE) of 0x00000000_00001000 is 0x80000000_00001000, the coherent cached
-direct-mapped VA (in XKPRANGE) of 0x00000000_00001000 is 0x90000000_00001000,
-and the weakly-ordered uncached direct-mapped VA (in XKPRANGE) of 0x00000000
-_00001000 is 0xA0000000_00001000.
-
-Relationship of Loongson and LoongArch
-======================================
-
-LoongArch is a RISC ISA which is different from any other existing ones, while
-Loongson is a family of processors. Loongson includes 3 series: Loongson-1 is
-the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series,
-and Loongson-3 is the high-end 64-bit processor series. Old Loongson is based on
-MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example:
-Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson-
-3A5000 (and future revisions) are all based on LoongArch.
-
-.. _loongarch-references:
-
-References
-==========
-
-Official web site of Loongson Technology Corp. Ltd.:
-
- http://www.loongson.cn/
-
-Developer web site of Loongson and LoongArch (Software and Documentation):
-
- http://www.loongnix.cn/
-
- https://github.com/loongson/
-
- https://loongson.github.io/LoongArch-Documentation/
-
-Documentation of LoongArch ISA:
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-CN.pdf (in Chinese)
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-EN.pdf (in English)
-
-Documentation of LoongArch ELF psABI:
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-CN.pdf (in Chinese)
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-EN.pdf (in English)
-
-Linux kernel repository of Loongson and LoongArch:
-
- https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-=======================================
-IRQ chip model (hierarchy) of LoongArch
-=======================================
-
-Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
-with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
-Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
-I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
-PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
-in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
-
-CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
-controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
-in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
-and there are two models of hierarchy (legacy model and extended model).
-
-Legacy IRQ model
-================
-
-In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
-to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
-interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
-to LIOINTC, and then CPUINTC::
-
- +-----+ +---------+ +-------+
- | IPI | --> | CPUINTC | <-- | Timer |
- +-----+ +---------+ +-------+
- ^
- |
- +---------+ +-------+
- | LIOINTC | <-- | UARTs |
- +---------+ +-------+
- ^
- |
- +-----------+
- | HTVECINTC |
- +-----------+
- ^ ^
- | |
- +---------+ +---------+
- | PCH-PIC | | PCH-MSI |
- +---------+ +---------+
- ^ ^ ^
- | | |
- +---------+ +---------+ +---------+
- | PCH-LPC | | Devices | | Devices |
- +---------+ +---------+ +---------+
- ^
- |
- +---------+
- | Devices |
- +---------+
-
-Extended IRQ model
-==================
-
-In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
-to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
-interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
-to CPUINTC directly::
-
- +-----+ +---------+ +-------+
- | IPI | --> | CPUINTC | <-- | Timer |
- +-----+ +---------+ +-------+
- ^ ^
- | |
- +---------+ +---------+ +-------+
- | EIOINTC | | LIOINTC | <-- | UARTs |
- +---------+ +---------+ +-------+
- ^ ^
- | |
- +---------+ +---------+
- | PCH-PIC | | PCH-MSI |
- +---------+ +---------+
- ^ ^ ^
- | | |
- +---------+ +---------+ +---------+
- | PCH-LPC | | Devices | | Devices |
- +---------+ +---------+ +---------+
- ^
- |
- +---------+
- | Devices |
- +---------+
-
-ACPI-related definitions
-========================
-
-CPUINTC::
-
- ACPI_MADT_TYPE_CORE_PIC;
- struct acpi_madt_core_pic;
- enum acpi_madt_core_pic_version;
-
-LIOINTC::
-
- ACPI_MADT_TYPE_LIO_PIC;
- struct acpi_madt_lio_pic;
- enum acpi_madt_lio_pic_version;
-
-EIOINTC::
-
- ACPI_MADT_TYPE_EIO_PIC;
- struct acpi_madt_eio_pic;
- enum acpi_madt_eio_pic_version;
-
-HTVECINTC::
-
- ACPI_MADT_TYPE_HT_PIC;
- struct acpi_madt_ht_pic;
- enum acpi_madt_ht_pic_version;
-
-PCH-PIC::
-
- ACPI_MADT_TYPE_BIO_PIC;
- struct acpi_madt_bio_pic;
- enum acpi_madt_bio_pic_version;
-
-PCH-MSI::
-
- ACPI_MADT_TYPE_MSI_PIC;
- struct acpi_madt_msi_pic;
- enum acpi_madt_msi_pic_version;
-
-PCH-LPC::
-
- ACPI_MADT_TYPE_LPC_PIC;
- struct acpi_madt_lpc_pic;
- enum acpi_madt_lpc_pic_version;
-
-References
-==========
-
-Documentation of Loongson-3A5000:
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)
-
-Documentation of Loongson's LS7A chipset:
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
-
-.. Note::
- - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
- in Section 7.4 of "LoongArch Reference Manual, Vol 1";
- - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
- "Loongson 3A5000 Processor Reference Manual";
- - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
- "Loongson 3A5000 Processor Reference Manual";
- - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
- "Loongson 3A5000 Processor Reference Manual";
- - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
- "Loongson 7A1000 Bridge User Manual";
- - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
- "Loongson 7A1000 Bridge User Manual".
../riscv/index
openrisc/index
parisc/index
- ../loongarch/index
+ loongarch/index
TODOList:
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+.. include:: ../../disclaimer-zh_CN.rst
+
+:Original: Documentation/arch/loongarch/booting.rst
+
+:翻译:
+
+ 司延腾 Yanteng Si <siyanteng@loongson.cn>
+
+====================
+启动 Linux/LoongArch
+====================
+
+:作者: 司延腾 <siyanteng@loongson.cn>
+:日期: 2022年11月18日
+
+BootLoader传递给内核的信息
+==========================
+
+LoongArch支持ACPI和FDT启动，需要传递给内核的信息包括memmap、initrd、cmdline、可
+选的ACPI/FDT表等。
+
+内核在 `kernel_entry` 入口处被传递以下参数:
+
+ - a0 = efi_boot: `efi_boot` 是一个标志，表示这个启动环境是否完全符合UEFI
+ 的要求。
+
+ - a1 = cmdline: `cmdline` 是一个指向内核命令行的指针。
+
+ - a2 = systemtable: `systemtable` 指向EFI的系统表，在这个阶段涉及的所有
+ 指针都是物理地址。
+
+Linux/LoongArch内核镜像文件头
+=============================
+
+内核镜像是EFI镜像。作为PE文件，它们有一个64字节的头部结构体，如下所示::
+
+ u32 MZ_MAGIC /* "MZ", MS-DOS 头 */
+ u32 res0 = 0 /* 保留 */
+ u64 kernel_entry /* 内核入口点 */
+ u64 _end - _text /* 内核镜像有效大小 */
+ u64 load_offset /* 加载内核镜像相对内存起始地址的偏移量 */
+ u64 res1 = 0 /* 保留 */
+ u64 res2 = 0 /* 保留 */
+ u64 res3 = 0 /* 保留 */
+ u32 LINUX_PE_MAGIC /* 魔术数 */
+ u32 pe_header - _head /* 到PE头的偏移量 */
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+.. include:: ../../disclaimer-zh_CN.rst
+
+:Original: Documentation/arch/loongarch/features.rst
+:Translator: Huacai Chen <chenhuacai@loongson.cn>
+
+.. kernel-feat:: $srctree/Documentation/features loongarch
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+.. include:: ../../disclaimer-zh_CN.rst
+
+:Original: Documentation/arch/loongarch/index.rst
+:Translator: Huacai Chen <chenhuacai@loongson.cn>
+
+=================
+LoongArch体系结构
+=================
+
+.. toctree::
+ :maxdepth: 2
+ :numbered:
+
+ introduction
+ booting
+ irq-chip-model
+
+ features
+
+.. only:: subproject and html
+
+ Indices
+ =======
+
+ * :ref:`genindex`
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+.. include:: ../../disclaimer-zh_CN.rst
+
+:Original: Documentation/arch/loongarch/introduction.rst
+:Translator: Huacai Chen <chenhuacai@loongson.cn>
+
+=============
+LoongArch介绍
+=============
+
+LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集
+包括一个精简32位版（LA32R）、一个标准32位版（LA32S）、一个64位版（LA64）。
+LoongArch定义了四个特权级（PLV0~PLV3），其中PLV0是最高特权级，用于内核；而PLV3
+是最低特权级，用于应用程序。本文档介绍了LoongArch的寄存器、基础指令集、虚拟内
+存以及其他一些主题。
+
+寄存器
+======
+
+LoongArch的寄存器包括通用寄存器（GPRs）、浮点寄存器（FPRs）、向量寄存器（VRs）
+和用于特权模式（PLV0）的控制状态寄存器（CSRs）。
+
+通用寄存器
+----------
+
+LoongArch包括32个通用寄存器（ ``$r0`` ~ ``$r31`` ），LA32中每个寄存器为32位宽，
+LA64中每个寄存器为64位宽。 ``$r0`` 的内容总是固定为0，而其他寄存器在体系结构层面
+没有特殊功能。（ ``$r1`` 算是一个例外，在BL指令中固定用作链接返回寄存器。）
+
+内核使用了一套LoongArch寄存器约定，定义在LoongArch ELF psABI规范中，详细描述参见
+:ref:`参考文献 <loongarch-references-zh_CN>`:
+
+================= =============== =================== ==========
+寄存器名 别名 用途 跨调用保持
+================= =============== =================== ==========
+``$r0`` ``$zero`` 常量0 不使用
+``$r1`` ``$ra`` 返回地址 否
+``$r2`` ``$tp`` TLS/线程信息指针 不使用
+``$r3`` ``$sp`` 栈指针 是
+``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否
+``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
+``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否
+``$r21`` ``$u0`` 每CPU变量基地址 不使用
+``$r22`` ``$fp`` 帧指针 是
+``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是
+================= =============== =================== ==========
+
+.. note::
+ 注意： ``$r21`` 寄存器在ELF psABI中保留未使用，但是在Linux内核用于保
+ 存每CPU变量基地址。该寄存器没有ABI命名，不过在内核中称为 ``$u0`` 。在
+ 一些遗留代码中有时可能见到 ``$v0`` 和 ``$v1`` ，它们是 ``$a0`` 和
+ ``$a1`` 的别名，属于已经废弃的用法。
+
+浮点寄存器
+----------
+
+当系统中存在FPU时，LoongArch有32个浮点寄存器（ ``$f0`` ~ ``$f31`` ）。在LA64
+的CPU核上，每个寄存器均为64位宽。
+
+浮点寄存器的使用约定与LoongArch ELF psABI规范的描述相同：
+
+================= ================== =================== ==========
+寄存器名 别名 用途 跨调用保持
+================= ================== =================== ==========
+``$f0``-``$f7`` ``$fa0``-``$fa7`` 参数寄存器 否
+``$f0``-``$f1`` ``$fv0``-``$fv1`` 返回值 否
+``$f8``-``$f23`` ``$ft0``-``$ft15`` 临时寄存器 否
+``$f24``-``$f31`` ``$fs0``-``$fs7`` 静态寄存器 是
+================= ================== =================== ==========
+
+.. note::
+ 注意：在一些遗留代码中有时可能见到 ``$fv0`` 和 ``$fv1`` ，它们是
+ ``$fa0`` 和 ``$fa1`` 的别名，属于已经废弃的用法。
+
+
+向量寄存器
+----------
+
+LoongArch现有两种向量扩展：
+
+- 128位向量扩展LSX（全称Loongson SIMD eXtention），
+- 256位向量扩展LASX（全称Loongson Advanced SIMD eXtention）。
+
+LSX使用 ``$v0`` ~ ``$v31`` 向量寄存器，而LASX则使用 ``$x0`` ~ ``$x31`` 。
+
+浮点寄存器和向量寄存器是复用的，比如：在一个实现了LSX和LASX的核上， ``$x0`` 的
+低128位与 ``$v0`` 共用， ``$v0`` 的低64位与 ``$f0`` 共用，其他寄存器依此类推。
+
+控制状态寄存器
+--------------
+
+控制状态寄存器只能在特权模式（PLV0）下访问:
+
+================= ==================================== ==========
+地址 全称描述 简称
+================= ==================================== ==========
+0x0 当前模式信息 CRMD
+0x1 异常前模式信息 PRMD
+0x2 扩展部件使能 EUEN
+0x3 杂项控制 MISC
+0x4 异常配置 ECFG
+0x5 异常状态 ESTAT
+0x6 异常返回地址 ERA
+0x7 出错(Faulting)虚拟地址 BADV
+0x8 出错(Faulting)指令字 BADI
+0xC 异常入口地址 EENTRY
+0x10 TLB索引 TLBIDX
+0x11 TLB表项高位 TLBEHI
+0x12 TLB表项低位0 TLBELO0
+0x13 TLB表项低位1 TLBELO1
+0x18 地址空间标识符 ASID
+0x19 低半地址空间页全局目录基址 PGDL
+0x1A 高半地址空间页全局目录基址 PGDH
+0x1B 页全局目录基址 PGD
+0x1C 页表遍历控制低半部分 PWCL
+0x1D 页表遍历控制高半部分 PWCH
+0x1E STLB页大小 STLBPS
+0x1F 缩减虚地址配置 RVACFG
+0x20 CPU编号 CPUID
+0x21 特权资源配置信息1 PRCFG1
+0x22 特权资源配置信息2 PRCFG2
+0x23 特权资源配置信息3 PRCFG3
+0x30+n (0≤n≤15) 数据保存寄存器 SAVEn
+0x40 定时器编号 TID
+0x41 定时器配置 TCFG
+0x42 定时器值 TVAL
+0x43 计时器补偿 CNTC
+0x44 定时器中断清除 TICLR
+0x60 LLBit相关控制 LLBCTL
+0x80 实现相关控制1 IMPCTL1
+0x81 实现相关控制2 IMPCTL2
+0x88 TLB重填异常入口地址 TLBRENTRY
+0x89 TLB重填异常出错(Faulting)虚地址 TLBRBADV
+0x8A TLB重填异常返回地址 TLBRERA
+0x8B TLB重填异常数据保存 TLBRSAVE
+0x8C TLB重填异常表项低位0 TLBRELO0
+0x8D TLB重填异常表项低位1 TLBRELO1
+0x8E TLB重填异常表项高位 TLBEHI
+0x8F TLB重填异常前模式信息 TLBRPRMD
+0x90 机器错误控制 MERRCTL
+0x91 机器错误信息1 MERRINFO1
+0x92 机器错误信息2 MERRINFO2
+0x93 机器错误异常入口地址 MERRENTRY
+0x94 机器错误异常返回地址 MERRERA
+0x95 机器错误异常数据保存 MERRSAVE
+0x98 高速缓存标签 CTAG
+0x180+n (0≤n≤3) 直接映射配置窗口n DMWn
+0x200+2n (0≤n≤31) 性能监测配置n PMCFGn
+0x201+2n (0≤n≤31) 性能监测计数器n PMCNTn
+0x300 内存读写监视点整体控制 MWPC
+0x301 内存读写监视点整体状态 MWPS
+0x310+8n (0≤n≤7) 内存读写监视点n配置1 MWPnCFG1
+0x311+8n (0≤n≤7) 内存读写监视点n配置2 MWPnCFG2
+0x312+8n (0≤n≤7) 内存读写监视点n配置3 MWPnCFG3
+0x313+8n (0≤n≤7) 内存读写监视点n配置4 MWPnCFG4
+0x380 取指监视点整体控制 FWPC
+0x381 取指监视点整体状态 FWPS
+0x390+8n (0≤n≤7) 取指监视点n配置1 FWPnCFG1
+0x391+8n (0≤n≤7) 取指监视点n配置2 FWPnCFG2
+0x392+8n (0≤n≤7) 取指监视点n配置3 FWPnCFG3
+0x393+8n (0≤n≤7) 取指监视点n配置4 FWPnCFG4
+0x500 调试寄存器 DBG
+0x501 调试异常返回地址 DERA
+0x502 调试数据保存 DSAVE
+================= ==================================== ==========
+
+ERA，TLBRERA，MERRERA和DERA有时也分别称为EPC，TLBREPC，MERREPC和DEPC。
+
+基础指令集
+==========
+
+指令格式
+--------
+
+LoongArch的指令字长为32位，一共有9种基本指令格式（以及一些变体）:
+
+=========== ==========================
+格式名称 指令构成
+=========== ==========================
+2R Opcode + Rj + Rd
+3R Opcode + Rk + Rj + Rd
+4R Opcode + Ra + Rk + Rj + Rd
+2RI8 Opcode + I8 + Rj + Rd
+2RI12 Opcode + I12 + Rj + Rd
+2RI14 Opcode + I14 + Rj + Rd
+2RI16 Opcode + I16 + Rj + Rd
+1RI21 Opcode + I21L + Rj + I21H
+I26 Opcode + I26L + I26H
+=========== ==========================
+
+Opcode是指令操作码，Rj和Rk是源操作数（寄存器），Rd是目标操作数（寄存器），Ra是
+4R-type格式特有的附加操作数（寄存器）。I8/I12/I14/I16/I21/I26分别是8位/12位/14位/
+16位/21位/26位的立即数。其中较长的21位和26位立即数在指令字中被分割为高位部分与低位
+部分，所以你们在这里的格式描述中能够看到I21L/I21H和I26L/I26H这样带后缀的表述。
+
+指令列表
+--------
+
+为了简便起见，我们在此只罗列一下指令名称（助记符），需要详细信息请阅读
+:ref:`参考文献 <loongarch-references-zh_CN>` 中的文档。
+
+1. 算术运算指令::
+
+ ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
+ SLT SLTU SLTI SLTUI
+ AND OR NOR XOR ANDN ORN ANDI ORI XORI
+ MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
+ MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
+ PCADDI PCADDU12I PCADDU18I
+ LU12I.W LU32I.D LU52I.D ADDU16I.D
+
+2. 移位运算指令::
+
+ SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
+ SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
+
+3. 位域操作指令::
+
+ EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
+ BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
+ REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
+ MASKEQZ MASKNEZ
+
+4. 分支转移指令::
+
+ BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
+
+5. 访存读写指令::
+
+ LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
+ LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
+ LDPTR.W LDPTR.D STPTR.W STPTR.D
+ PRELD PRELDX
+
+6. 原子操作指令::
+
+ LL.W SC.W LL.D SC.D
+ AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
+ AMMAX.W AMMAX.D AMMIN.W AMMIN.D
+
+7. 栅障指令::
+
+ IBAR DBAR
+
+8. 特殊指令::
+
+ SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D
+ ASRTLE.D ASRTGT.D
+
+9. 特权指令::
+
+ CSRRD CSRWR CSRXCHG
+ IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
+ CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
+
+虚拟内存
+========
+
+LoongArch可以使用直接映射虚拟内存和分页映射虚拟内存。
+
+直接映射虚拟内存通过CSR.DMWn（n=0~3）来进行配置，虚拟地址（VA）和物理地址（PA）
+之间有简单的映射关系::
+
+ VA = PA + 固定偏移
+
+分页映射的虚拟地址（VA）和物理地址（PA）有任意的映射关系，这种关系记录在TLB和页
+表中。LoongArch的TLB包括一个全相联的MTLB（Multiple Page Size TLB，多样页大小TLB）
+和一个组相联的STLB（Single Page Size TLB，单一页大小TLB）。
+
+缺省状态下，LA32的整个虚拟地址空间配置如下：
+
+============ =========================== ===========================
+区段名 地址范围 属性
+============ =========================== ===========================
+``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` 分页映射, 可缓存, PLV0~3
+``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` 直接映射, 非缓存, PLV0
+``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` 直接映射, 可缓存, PLV0
+``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` 分页映射, 可缓存, PLV0
+============ =========================== ===========================
+
+用户态（PLV3）只能访问UVRANGE，对于直接映射的KPRANGE0和KPRANGE1，将虚拟地址的第
+30~31位清零就等于物理地址。例如：物理地址0x00001000对应的非缓存直接映射虚拟地址
+是0x80001000，而其可缓存直接映射虚拟地址是0xA0001000。
+
+缺省状态下，LA64的整个虚拟地址空间配置如下：
+
+============ ====================== ==================================
+区段名 地址范围 属性
+============ ====================== ==================================
+``XUVRANGE`` ``0x0000000000000000 - 分页映射, 可缓存, PLV0~3
+ 0x3FFFFFFFFFFFFFFF``
+``XSPRANGE`` ``0x4000000000000000 - 直接映射, 可缓存 / 非缓存, PLV0
+ 0x7FFFFFFFFFFFFFFF``
+``XKPRANGE`` ``0x8000000000000000 - 直接映射, 可缓存 / 非缓存, PLV0
+ 0xBFFFFFFFFFFFFFFF``
+``XKVRANGE`` ``0xC000000000000000 - 分页映射, 可缓存, PLV0
+ 0xFFFFFFFFFFFFFFFF``
+============ ====================== ==================================
+
+用户态（PLV3）只能访问XUVRANGE，对于直接映射的XSPRANGE和XKPRANGE，将虚拟地址的第
+60~63位清零就等于物理地址，而其缓存属性是通过虚拟地址的第60~61位配置的（0表示强序
+非缓存，1表示一致可缓存，2表示弱序非缓存）。
+
+目前，我们仅用XKPRANGE来进行直接映射，XSPRANGE保留给以后用。
+
+此处给出一个直接映射的例子：物理地址0x00000000_00001000的强序非缓存直接映射虚拟地址
+（在XKPRANGE中）是0x80000000_00001000，其一致可缓存直接映射虚拟地址（在XKPRANGE中）
+是0x90000000_00001000，而其弱序非缓存直接映射虚拟地址（在XKPRANGE中）是0xA0000000_
+00001000。
+
+Loongson与LoongArch的关系
+=========================
+
+LoongArch是一种RISC指令集架构（ISA），不同于现存的任何一种ISA，而Loongson（即龙
+芯）是一个处理器家族。龙芯包括三个系列：Loongson-1（龙芯1号）是32位处理器系列，
+Loongson-2（龙芯2号）是低端64位处理器系列，而Loongson-3（龙芯3号）是高端64位处理
+器系列。旧的龙芯处理器基于MIPS架构，而新的龙芯处理器基于LoongArch架构。以龙芯3号
+为例：龙芯3A1000/3B1500/3A2000/3A3000/3A4000都是兼容MIPS的，而龙芯3A5000（以及将
+来的型号）都是基于LoongArch的。
+
+.. _loongarch-references-zh_CN:
+
+参考文献
+========
+
+Loongson官方网站（龙芯中科技术股份有限公司）：
+
+ http://www.loongson.cn/
+
+Loongson与LoongArch的开发者网站（软件与文档资源）：
+
+ http://www.loongnix.cn/
+
+ https://github.com/loongson/
+
+ https://loongson.github.io/LoongArch-Documentation/
+
+LoongArch指令集架构的文档：
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-CN.pdf （中文版）
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-EN.pdf （英文版）
+
+LoongArch的ELF psABI文档：
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-CN.pdf （中文版）
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-EN.pdf （英文版）
+
+Loongson与LoongArch的Linux内核源码仓库：
+
+ https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0
+
+.. include:: ../../disclaimer-zh_CN.rst
+
+:Original: Documentation/arch/loongarch/irq-chip-model.rst
+:Translator: Huacai Chen <chenhuacai@loongson.cn>
+
+==================================
+LoongArch的IRQ芯片模型（层级关系）
+==================================
+
+目前，基于LoongArch的处理器（如龙芯3A5000）只能与LS7A芯片组配合工作。LoongArch计算机
+中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
+Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
+HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
+断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
+
+CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的
+全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
+断控制器（在配套芯片组里面）。这些中断控制器（或者说IRQ芯片）以一种层次树的组织形式
+级联在一起，一共有两种层级关系模型（传统IRQ模型和扩展IRQ模型）。
+
+传统IRQ模型
+===========
+
+在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
+CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
+PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
+
+ +-----+ +---------+ +-------+
+ | IPI | --> | CPUINTC | <-- | Timer |
+ +-----+ +---------+ +-------+
+ ^
+ |
+ +---------+ +-------+
+ | LIOINTC | <-- | UARTs |
+ +---------+ +-------+
+ ^
+ |
+ +-----------+
+ | HTVECINTC |
+ +-----------+
+ ^ ^
+ | |
+ +---------+ +---------+
+ | PCH-PIC | | PCH-MSI |
+ +---------+ +---------+
+ ^ ^ ^
+ | | |
+ +---------+ +---------+ +---------+
+ | PCH-LPC | | Devices | | Devices |
+ +---------+ +---------+ +---------+
+ ^
+ |
+ +---------+
+ | Devices |
+ +---------+
+
+扩展IRQ模型
+===========
+
+在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
+CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
+PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
+
+ +-----+ +---------+ +-------+
+ | IPI | --> | CPUINTC | <-- | Timer |
+ +-----+ +---------+ +-------+
+ ^ ^
+ | |
+ +---------+ +---------+ +-------+
+ | EIOINTC | | LIOINTC | <-- | UARTs |
+ +---------+ +---------+ +-------+
+ ^ ^
+ | |
+ +---------+ +---------+
+ | PCH-PIC | | PCH-MSI |
+ +---------+ +---------+
+ ^ ^ ^
+ | | |
+ +---------+ +---------+ +---------+
+ | PCH-LPC | | Devices | | Devices |
+ +---------+ +---------+ +---------+
+ ^
+ |
+ +---------+
+ | Devices |
+ +---------+
+
+ACPI相关的定义
+==============
+
+CPUINTC::
+
+ ACPI_MADT_TYPE_CORE_PIC;
+ struct acpi_madt_core_pic;
+ enum acpi_madt_core_pic_version;
+
+LIOINTC::
+
+ ACPI_MADT_TYPE_LIO_PIC;
+ struct acpi_madt_lio_pic;
+ enum acpi_madt_lio_pic_version;
+
+EIOINTC::
+
+ ACPI_MADT_TYPE_EIO_PIC;
+ struct acpi_madt_eio_pic;
+ enum acpi_madt_eio_pic_version;
+
+HTVECINTC::
+
+ ACPI_MADT_TYPE_HT_PIC;
+ struct acpi_madt_ht_pic;
+ enum acpi_madt_ht_pic_version;
+
+PCH-PIC::
+
+ ACPI_MADT_TYPE_BIO_PIC;
+ struct acpi_madt_bio_pic;
+ enum acpi_madt_bio_pic_version;
+
+PCH-MSI::
+
+ ACPI_MADT_TYPE_MSI_PIC;
+ struct acpi_madt_msi_pic;
+ enum acpi_madt_msi_pic_version;
+
+PCH-LPC::
+
+ ACPI_MADT_TYPE_LPC_PIC;
+ struct acpi_madt_lpc_pic;
+ enum acpi_madt_lpc_pic_version;
+
+参考文献
+========
+
+龙芯3A5000的文档：
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (中文版)
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (英文版)
+
+龙芯LS7A芯片组的文档：
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (中文版)
+
+ https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (英文版)
+
+.. note::
+ - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
+ 中断控制逻辑；
+ - LIOINTC：即《龙芯3A5000处理器使用手册》第11.1节所描述的“传统I/O中断”；
+ - EIOINTC：即《龙芯3A5000处理器使用手册》第11.2节所描述的“扩展I/O中断”；
+ - HTVECINTC：即《龙芯3A5000处理器使用手册》第14.3节所描述的“HyperTransport中断”；
+ - PCH-PIC/PCH-MSI：即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”；
+ - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-.. include:: ../disclaimer-zh_CN.rst
-
-:Original: Documentation/loongarch/booting.rst
-
-:翻译:
-
- 司延腾 Yanteng Si <siyanteng@loongson.cn>
-
-====================
-启动 Linux/LoongArch
-====================
-
-:作者: 司延腾 <siyanteng@loongson.cn>
-:日期: 2022年11月18日
-
-BootLoader传递给内核的信息
-==========================
-
-LoongArch支持ACPI和FDT启动，需要传递给内核的信息包括memmap、initrd、cmdline、可
-选的ACPI/FDT表等。
-
-内核在 `kernel_entry` 入口处被传递以下参数:
-
- - a0 = efi_boot: `efi_boot` 是一个标志，表示这个启动环境是否完全符合UEFI
- 的要求。
-
- - a1 = cmdline: `cmdline` 是一个指向内核命令行的指针。
-
- - a2 = systemtable: `systemtable` 指向EFI的系统表，在这个阶段涉及的所有
- 指针都是物理地址。
-
-Linux/LoongArch内核镜像文件头
-=============================
-
-内核镜像是EFI镜像。作为PE文件，它们有一个64字节的头部结构体，如下所示::
-
- u32 MZ_MAGIC /* "MZ", MS-DOS 头 */
- u32 res0 = 0 /* 保留 */
- u64 kernel_entry /* 内核入口点 */
- u64 _end - _text /* 内核镜像有效大小 */
- u64 load_offset /* 加载内核镜像相对内存起始地址的偏移量 */
- u64 res1 = 0 /* 保留 */
- u64 res2 = 0 /* 保留 */
- u64 res3 = 0 /* 保留 */
- u32 LINUX_PE_MAGIC /* 魔术数 */
- u32 pe_header - _head /* 到PE头的偏移量 */
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-.. include:: ../disclaimer-zh_CN.rst
-
-:Original: Documentation/loongarch/features.rst
-:Translator: Huacai Chen <chenhuacai@loongson.cn>
-
-.. kernel-feat:: $srctree/Documentation/features loongarch
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-.. include:: ../disclaimer-zh_CN.rst
-
-:Original: Documentation/loongarch/index.rst
-:Translator: Huacai Chen <chenhuacai@loongson.cn>
-
-=================
-LoongArch体系结构
-=================
-
-.. toctree::
- :maxdepth: 2
- :numbered:
-
- introduction
- booting
- irq-chip-model
-
- features
-
-.. only:: subproject and html
-
- Indices
- =======
-
- * :ref:`genindex`
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-.. include:: ../disclaimer-zh_CN.rst
-
-:Original: Documentation/loongarch/introduction.rst
-:Translator: Huacai Chen <chenhuacai@loongson.cn>
-
-=============
-LoongArch介绍
-=============
-
-LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集
-包括一个精简32位版（LA32R）、一个标准32位版（LA32S）、一个64位版（LA64）。
-LoongArch定义了四个特权级（PLV0~PLV3），其中PLV0是最高特权级，用于内核；而PLV3
-是最低特权级，用于应用程序。本文档介绍了LoongArch的寄存器、基础指令集、虚拟内
-存以及其他一些主题。
-
-寄存器
-======
-
-LoongArch的寄存器包括通用寄存器（GPRs）、浮点寄存器（FPRs）、向量寄存器（VRs）
-和用于特权模式（PLV0）的控制状态寄存器（CSRs）。
-
-通用寄存器
-----------
-
-LoongArch包括32个通用寄存器（ ``$r0`` ~ ``$r31`` ），LA32中每个寄存器为32位宽，
-LA64中每个寄存器为64位宽。 ``$r0`` 的内容总是固定为0，而其他寄存器在体系结构层面
-没有特殊功能。（ ``$r1`` 算是一个例外，在BL指令中固定用作链接返回寄存器。）
-
-内核使用了一套LoongArch寄存器约定，定义在LoongArch ELF psABI规范中，详细描述参见
-:ref:`参考文献 <loongarch-references-zh_CN>`:
-
-================= =============== =================== ==========
-寄存器名 别名 用途 跨调用保持
-================= =============== =================== ==========
-``$r0`` ``$zero`` 常量0 不使用
-``$r1`` ``$ra`` 返回地址 否
-``$r2`` ``$tp`` TLS/线程信息指针 不使用
-``$r3`` ``$sp`` 栈指针 是
-``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否
-``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
-``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否
-``$r21`` ``$u0`` 每CPU变量基地址 不使用
-``$r22`` ``$fp`` 帧指针 是
-``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是
-================= =============== =================== ==========
-
-.. note::
- 注意： ``$r21`` 寄存器在ELF psABI中保留未使用，但是在Linux内核用于保
- 存每CPU变量基地址。该寄存器没有ABI命名，不过在内核中称为 ``$u0`` 。在
- 一些遗留代码中有时可能见到 ``$v0`` 和 ``$v1`` ，它们是 ``$a0`` 和
- ``$a1`` 的别名，属于已经废弃的用法。
-
-浮点寄存器
-----------
-
-当系统中存在FPU时，LoongArch有32个浮点寄存器（ ``$f0`` ~ ``$f31`` ）。在LA64
-的CPU核上，每个寄存器均为64位宽。
-
-浮点寄存器的使用约定与LoongArch ELF psABI规范的描述相同：
-
-================= ================== =================== ==========
-寄存器名 别名 用途 跨调用保持
-================= ================== =================== ==========
-``$f0``-``$f7`` ``$fa0``-``$fa7`` 参数寄存器 否
-``$f0``-``$f1`` ``$fv0``-``$fv1`` 返回值 否
-``$f8``-``$f23`` ``$ft0``-``$ft15`` 临时寄存器 否
-``$f24``-``$f31`` ``$fs0``-``$fs7`` 静态寄存器 是
-================= ================== =================== ==========
-
-.. note::
- 注意：在一些遗留代码中有时可能见到 ``$fv0`` 和 ``$fv1`` ，它们是
- ``$fa0`` 和 ``$fa1`` 的别名，属于已经废弃的用法。
-
-
-向量寄存器
-----------
-
-LoongArch现有两种向量扩展：
-
-- 128位向量扩展LSX（全称Loongson SIMD eXtention），
-- 256位向量扩展LASX（全称Loongson Advanced SIMD eXtention）。
-
-LSX使用 ``$v0`` ~ ``$v31`` 向量寄存器，而LASX则使用 ``$x0`` ~ ``$x31`` 。
-
-浮点寄存器和向量寄存器是复用的，比如：在一个实现了LSX和LASX的核上， ``$x0`` 的
-低128位与 ``$v0`` 共用， ``$v0`` 的低64位与 ``$f0`` 共用，其他寄存器依此类推。
-
-控制状态寄存器
---------------
-
-控制状态寄存器只能在特权模式（PLV0）下访问:
-
-================= ==================================== ==========
-地址 全称描述 简称
-================= ==================================== ==========
-0x0 当前模式信息 CRMD
-0x1 异常前模式信息 PRMD
-0x2 扩展部件使能 EUEN
-0x3 杂项控制 MISC
-0x4 异常配置 ECFG
-0x5 异常状态 ESTAT
-0x6 异常返回地址 ERA
-0x7 出错(Faulting)虚拟地址 BADV
-0x8 出错(Faulting)指令字 BADI
-0xC 异常入口地址 EENTRY
-0x10 TLB索引 TLBIDX
-0x11 TLB表项高位 TLBEHI
-0x12 TLB表项低位0 TLBELO0
-0x13 TLB表项低位1 TLBELO1
-0x18 地址空间标识符 ASID
-0x19 低半地址空间页全局目录基址 PGDL
-0x1A 高半地址空间页全局目录基址 PGDH
-0x1B 页全局目录基址 PGD
-0x1C 页表遍历控制低半部分 PWCL
-0x1D 页表遍历控制高半部分 PWCH
-0x1E STLB页大小 STLBPS
-0x1F 缩减虚地址配置 RVACFG
-0x20 CPU编号 CPUID
-0x21 特权资源配置信息1 PRCFG1
-0x22 特权资源配置信息2 PRCFG2
-0x23 特权资源配置信息3 PRCFG3
-0x30+n (0≤n≤15) 数据保存寄存器 SAVEn
-0x40 定时器编号 TID
-0x41 定时器配置 TCFG
-0x42 定时器值 TVAL
-0x43 计时器补偿 CNTC
-0x44 定时器中断清除 TICLR
-0x60 LLBit相关控制 LLBCTL
-0x80 实现相关控制1 IMPCTL1
-0x81 实现相关控制2 IMPCTL2
-0x88 TLB重填异常入口地址 TLBRENTRY
-0x89 TLB重填异常出错(Faulting)虚地址 TLBRBADV
-0x8A TLB重填异常返回地址 TLBRERA
-0x8B TLB重填异常数据保存 TLBRSAVE
-0x8C TLB重填异常表项低位0 TLBRELO0
-0x8D TLB重填异常表项低位1 TLBRELO1
-0x8E TLB重填异常表项高位 TLBEHI
-0x8F TLB重填异常前模式信息 TLBRPRMD
-0x90 机器错误控制 MERRCTL
-0x91 机器错误信息1 MERRINFO1
-0x92 机器错误信息2 MERRINFO2
-0x93 机器错误异常入口地址 MERRENTRY
-0x94 机器错误异常返回地址 MERRERA
-0x95 机器错误异常数据保存 MERRSAVE
-0x98 高速缓存标签 CTAG
-0x180+n (0≤n≤3) 直接映射配置窗口n DMWn
-0x200+2n (0≤n≤31) 性能监测配置n PMCFGn
-0x201+2n (0≤n≤31) 性能监测计数器n PMCNTn
-0x300 内存读写监视点整体控制 MWPC
-0x301 内存读写监视点整体状态 MWPS
-0x310+8n (0≤n≤7) 内存读写监视点n配置1 MWPnCFG1
-0x311+8n (0≤n≤7) 内存读写监视点n配置2 MWPnCFG2
-0x312+8n (0≤n≤7) 内存读写监视点n配置3 MWPnCFG3
-0x313+8n (0≤n≤7) 内存读写监视点n配置4 MWPnCFG4
-0x380 取指监视点整体控制 FWPC
-0x381 取指监视点整体状态 FWPS
-0x390+8n (0≤n≤7) 取指监视点n配置1 FWPnCFG1
-0x391+8n (0≤n≤7) 取指监视点n配置2 FWPnCFG2
-0x392+8n (0≤n≤7) 取指监视点n配置3 FWPnCFG3
-0x393+8n (0≤n≤7) 取指监视点n配置4 FWPnCFG4
-0x500 调试寄存器 DBG
-0x501 调试异常返回地址 DERA
-0x502 调试数据保存 DSAVE
-================= ==================================== ==========
-
-ERA，TLBRERA，MERRERA和DERA有时也分别称为EPC，TLBREPC，MERREPC和DEPC。
-
-基础指令集
-==========
-
-指令格式
---------
-
-LoongArch的指令字长为32位，一共有9种基本指令格式（以及一些变体）:
-
-=========== ==========================
-格式名称 指令构成
-=========== ==========================
-2R Opcode + Rj + Rd
-3R Opcode + Rk + Rj + Rd
-4R Opcode + Ra + Rk + Rj + Rd
-2RI8 Opcode + I8 + Rj + Rd
-2RI12 Opcode + I12 + Rj + Rd
-2RI14 Opcode + I14 + Rj + Rd
-2RI16 Opcode + I16 + Rj + Rd
-1RI21 Opcode + I21L + Rj + I21H
-I26 Opcode + I26L + I26H
-=========== ==========================
-
-Opcode是指令操作码，Rj和Rk是源操作数（寄存器），Rd是目标操作数（寄存器），Ra是
-4R-type格式特有的附加操作数（寄存器）。I8/I12/I14/I16/I21/I26分别是8位/12位/14位/
-16位/21位/26位的立即数。其中较长的21位和26位立即数在指令字中被分割为高位部分与低位
-部分，所以你们在这里的格式描述中能够看到I21L/I21H和I26L/I26H这样带后缀的表述。
-
-指令列表
---------
-
-为了简便起见，我们在此只罗列一下指令名称（助记符），需要详细信息请阅读
-:ref:`参考文献 <loongarch-references-zh_CN>` 中的文档。
-
-1. 算术运算指令::
-
- ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
- SLT SLTU SLTI SLTUI
- AND OR NOR XOR ANDN ORN ANDI ORI XORI
- MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
- MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
- PCADDI PCADDU12I PCADDU18I
- LU12I.W LU32I.D LU52I.D ADDU16I.D
-
-2. 移位运算指令::
-
- SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
- SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
-
-3. 位域操作指令::
-
- EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
- BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
- REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
- MASKEQZ MASKNEZ
-
-4. 分支转移指令::
-
- BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
-
-5. 访存读写指令::
-
- LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
- LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
- LDPTR.W LDPTR.D STPTR.W STPTR.D
- PRELD PRELDX
-
-6. 原子操作指令::
-
- LL.W SC.W LL.D SC.D
- AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
- AMMAX.W AMMAX.D AMMIN.W AMMIN.D
-
-7. 栅障指令::
-
- IBAR DBAR
-
-8. 特殊指令::
-
- SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D
- ASRTLE.D ASRTGT.D
-
-9. 特权指令::
-
- CSRRD CSRWR CSRXCHG
- IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
- CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
-
-虚拟内存
-========
-
-LoongArch可以使用直接映射虚拟内存和分页映射虚拟内存。
-
-直接映射虚拟内存通过CSR.DMWn（n=0~3）来进行配置，虚拟地址（VA）和物理地址（PA）
-之间有简单的映射关系::
-
- VA = PA + 固定偏移
-
-分页映射的虚拟地址（VA）和物理地址（PA）有任意的映射关系，这种关系记录在TLB和页
-表中。LoongArch的TLB包括一个全相联的MTLB（Multiple Page Size TLB，多样页大小TLB）
-和一个组相联的STLB（Single Page Size TLB，单一页大小TLB）。
-
-缺省状态下，LA32的整个虚拟地址空间配置如下：
-
-============ =========================== ===========================
-区段名 地址范围 属性
-============ =========================== ===========================
-``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` 分页映射, 可缓存, PLV0~3
-``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` 直接映射, 非缓存, PLV0
-``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` 直接映射, 可缓存, PLV0
-``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` 分页映射, 可缓存, PLV0
-============ =========================== ===========================
-
-用户态（PLV3）只能访问UVRANGE，对于直接映射的KPRANGE0和KPRANGE1，将虚拟地址的第
-30~31位清零就等于物理地址。例如：物理地址0x00001000对应的非缓存直接映射虚拟地址
-是0x80001000，而其可缓存直接映射虚拟地址是0xA0001000。
-
-缺省状态下，LA64的整个虚拟地址空间配置如下：
-
-============ ====================== ==================================
-区段名 地址范围 属性
-============ ====================== ==================================
-``XUVRANGE`` ``0x0000000000000000 - 分页映射, 可缓存, PLV0~3
- 0x3FFFFFFFFFFFFFFF``
-``XSPRANGE`` ``0x4000000000000000 - 直接映射, 可缓存 / 非缓存, PLV0
- 0x7FFFFFFFFFFFFFFF``
-``XKPRANGE`` ``0x8000000000000000 - 直接映射, 可缓存 / 非缓存, PLV0
- 0xBFFFFFFFFFFFFFFF``
-``XKVRANGE`` ``0xC000000000000000 - 分页映射, 可缓存, PLV0
- 0xFFFFFFFFFFFFFFFF``
-============ ====================== ==================================
-
-用户态（PLV3）只能访问XUVRANGE，对于直接映射的XSPRANGE和XKPRANGE，将虚拟地址的第
-60~63位清零就等于物理地址，而其缓存属性是通过虚拟地址的第60~61位配置的（0表示强序
-非缓存，1表示一致可缓存，2表示弱序非缓存）。
-
-目前，我们仅用XKPRANGE来进行直接映射，XSPRANGE保留给以后用。
-
-此处给出一个直接映射的例子：物理地址0x00000000_00001000的强序非缓存直接映射虚拟地址
-（在XKPRANGE中）是0x80000000_00001000，其一致可缓存直接映射虚拟地址（在XKPRANGE中）
-是0x90000000_00001000，而其弱序非缓存直接映射虚拟地址（在XKPRANGE中）是0xA0000000_
-00001000。
-
-Loongson与LoongArch的关系
-=========================
-
-LoongArch是一种RISC指令集架构（ISA），不同于现存的任何一种ISA，而Loongson（即龙
-芯）是一个处理器家族。龙芯包括三个系列：Loongson-1（龙芯1号）是32位处理器系列，
-Loongson-2（龙芯2号）是低端64位处理器系列，而Loongson-3（龙芯3号）是高端64位处理
-器系列。旧的龙芯处理器基于MIPS架构，而新的龙芯处理器基于LoongArch架构。以龙芯3号
-为例：龙芯3A1000/3B1500/3A2000/3A3000/3A4000都是兼容MIPS的，而龙芯3A5000（以及将
-来的型号）都是基于LoongArch的。
-
-.. _loongarch-references-zh_CN:
-
-参考文献
-========
-
-Loongson官方网站（龙芯中科技术股份有限公司）：
-
- http://www.loongson.cn/
-
-Loongson与LoongArch的开发者网站（软件与文档资源）：
-
- http://www.loongnix.cn/
-
- https://github.com/loongson/
-
- https://loongson.github.io/LoongArch-Documentation/
-
-LoongArch指令集架构的文档：
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-CN.pdf （中文版）
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-EN.pdf （英文版）
-
-LoongArch的ELF psABI文档：
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-CN.pdf （中文版）
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-EN.pdf （英文版）
-
-Loongson与LoongArch的Linux内核源码仓库：
-
- https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0
-
-.. include:: ../disclaimer-zh_CN.rst
-
-:Original: Documentation/loongarch/irq-chip-model.rst
-:Translator: Huacai Chen <chenhuacai@loongson.cn>
-
-==================================
-LoongArch的IRQ芯片模型（层级关系）
-==================================
-
-目前，基于LoongArch的处理器（如龙芯3A5000）只能与LS7A芯片组配合工作。LoongArch计算机
-中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
-Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
-HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
-断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
-
-CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的
-全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
-断控制器（在配套芯片组里面）。这些中断控制器（或者说IRQ芯片）以一种层次树的组织形式
-级联在一起，一共有两种层级关系模型（传统IRQ模型和扩展IRQ模型）。
-
-传统IRQ模型
-===========
-
-在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
-CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
-PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
-
- +-----+ +---------+ +-------+
- | IPI | --> | CPUINTC | <-- | Timer |
- +-----+ +---------+ +-------+
- ^
- |
- +---------+ +-------+
- | LIOINTC | <-- | UARTs |
- +---------+ +-------+
- ^
- |
- +-----------+
- | HTVECINTC |
- +-----------+
- ^ ^
- | |
- +---------+ +---------+
- | PCH-PIC | | PCH-MSI |
- +---------+ +---------+
- ^ ^ ^
- | | |
- +---------+ +---------+ +---------+
- | PCH-LPC | | Devices | | Devices |
- +---------+ +---------+ +---------+
- ^
- |
- +---------+
- | Devices |
- +---------+
-
-扩展IRQ模型
-===========
-
-在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
-CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
-PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
-
- +-----+ +---------+ +-------+
- | IPI | --> | CPUINTC | <-- | Timer |
- +-----+ +---------+ +-------+
- ^ ^
- | |
- +---------+ +---------+ +-------+
- | EIOINTC | | LIOINTC | <-- | UARTs |
- +---------+ +---------+ +-------+
- ^ ^
- | |
- +---------+ +---------+
- | PCH-PIC | | PCH-MSI |
- +---------+ +---------+
- ^ ^ ^
- | | |
- +---------+ +---------+ +---------+
- | PCH-LPC | | Devices | | Devices |
- +---------+ +---------+ +---------+
- ^
- |
- +---------+
- | Devices |
- +---------+
-
-ACPI相关的定义
-==============
-
-CPUINTC::
-
- ACPI_MADT_TYPE_CORE_PIC;
- struct acpi_madt_core_pic;
- enum acpi_madt_core_pic_version;
-
-LIOINTC::
-
- ACPI_MADT_TYPE_LIO_PIC;
- struct acpi_madt_lio_pic;
- enum acpi_madt_lio_pic_version;
-
-EIOINTC::
-
- ACPI_MADT_TYPE_EIO_PIC;
- struct acpi_madt_eio_pic;
- enum acpi_madt_eio_pic_version;
-
-HTVECINTC::
-
- ACPI_MADT_TYPE_HT_PIC;
- struct acpi_madt_ht_pic;
- enum acpi_madt_ht_pic_version;
-
-PCH-PIC::
-
- ACPI_MADT_TYPE_BIO_PIC;
- struct acpi_madt_bio_pic;
- enum acpi_madt_bio_pic_version;
-
-PCH-MSI::
-
- ACPI_MADT_TYPE_MSI_PIC;
- struct acpi_madt_msi_pic;
- enum acpi_madt_msi_pic_version;
-
-PCH-LPC::
-
- ACPI_MADT_TYPE_LPC_PIC;
- struct acpi_madt_lpc_pic;
- enum acpi_madt_lpc_pic_version;
-
-参考文献
-========
-
-龙芯3A5000的文档：
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (中文版)
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (英文版)
-
-龙芯LS7A芯片组的文档：
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (中文版)
-
- https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (英文版)
-
-.. note::
- - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
- 中断控制逻辑；
- - LIOINTC：即《龙芯3A5000处理器使用手册》第11.1节所描述的“传统I/O中断”；
- - EIOINTC：即《龙芯3A5000处理器使用手册》第11.2节所描述的“扩展I/O中断”；
- - HTVECINTC：即《龙芯3A5000处理器使用手册》第14.3节所描述的“HyperTransport中断”；
- - PCH-PIC/PCH-MSI：即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”；
- - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。
L: loongarch@lists.linux.dev
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
-F: Documentation/loongarch/
-F: Documentation/translations/zh_CN/loongarch/
+F: Documentation/arch/loongarch/
+F: Documentation/translations/zh_CN/arch/loongarch/
F: arch/loongarch/
F: drivers/*/*loongarch*
help
Support for the LoongArch CPU Interrupt Controller. For details of
irq chip hierarchy on LoongArch platforms please read the document
- Documentation/loongarch/irq-chip-model.rst.
+ Documentation/arch/loongarch/irq-chip-model.rst.
config LOONGSON_LIOINTC
bool "Loongson Local I/O Interrupt Controller"
projects / linux.git / commitdiff