drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset

Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C
behavior. If we do not properly reset them, we would miss delivery of
interrupts if a pending bit is set when enabling IRQs.

As an example, the display part of our probe routine contains paths
where we wait for vblank interrupts. If a display interrupt was already
pending when enabling IRQs, we would time out waiting for the vblank.

That in fact happened recently when modprobing Xe on a Lunar Lake with a
specific configuration; and that's how we found out we were missing this
step in the IRQ enabling logic.

Fix the issue by clearing GFX_MSTR_IRQ as part of the IRQ reset.

v2:
  - Make resetting GFX_MSTR_IRQ be the last step to avoid bit
    re-latching. (Ville)
v3:
  - Swap nesting order: guard loop with the IP version check instead of
    doing the check at each iteration. (Lucas)
v4:
  - Add braces for the "if" statement guarding the loop to make the
    compiler happy. (Gustavo)

BSpec: 50875, 54028, 62357
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230926221914.106843-2-gustavo.sousa@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index a91e782e06ebf739dcf3c9e554905d2b10f70eec..4cc5f7086b4ceae6c334c3317563a326f49fe2c4 100644 (file)
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -511,6 +511,13 @@ static void dg1_irq_reset(struct xe_tile *tile)
        mask_and_disable(tile, PCU_IRQ_OFFSET);
 }
 
+static void dg1_irq_reset_mstr(struct xe_tile *tile)
+{
+       struct xe_gt *mmio = tile->primary_gt;
+
+       xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0);
+}
+
 static void xe_irq_reset(struct xe_device *xe)
 {
        struct xe_tile *tile;
@@ -525,6 +532,16 @@ static void xe_irq_reset(struct xe_device *xe)
 
        tile = xe_device_get_root_tile(xe);
        mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
+
+       /*
+        * The tile's top-level status register should be the last one
+        * to be reset to avoid possible bit re-latching from lower
+        * level interrupts.
+        */
+       if (GRAPHICS_VERx100(xe) >= 1210) {
+               for_each_tile(tile, xe, id)
+                       dg1_irq_reset_mstr(tile);
+       }
 }
 
 static void xe_irq_postinstall(struct xe_device *xe)