dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
authorSam Protsenko <semen.protsenko@linaro.org>
Thu, 23 Feb 2023 04:21:28 +0000 (22:21 -0600)
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Mon, 6 Mar 2023 15:53:07 +0000 (16:53 +0100)
CMU_G3D generates Gondul GPU and bus clocks for BLK_G3D.
Add clock indices and binding documentation for CMU_G3D.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223042133.26551-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
include/dt-bindings/clock/exynos850.h

index 141cf173f87d48f4ee9bcc7d42ef468ce14402f2..8aa87b8c1b33018f3f2b9d228688852fb4b2b3ec 100644 (file)
@@ -37,6 +37,7 @@ properties:
       - samsung,exynos850-cmu-cmgp
       - samsung,exynos850-cmu-core
       - samsung,exynos850-cmu-dpu
+      - samsung,exynos850-cmu-g3d
       - samsung,exynos850-cmu-hsi
       - samsung,exynos850-cmu-is
       - samsung,exynos850-cmu-mfcmscl
@@ -169,6 +170,24 @@ allOf:
             - const: oscclk
             - const: dout_dpu
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-g3d
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: G3D clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_g3d_switch
+
   - if:
       properties:
         compatible:
index 88d5289883d38361a1250d0856e035705134a890..8bb62e43fd608cac981398661a123ff6c36d7a7c 100644 (file)
 #define CLK_DOUT_MFCMSCL_M2M           73
 #define CLK_DOUT_MFCMSCL_MCSC          74
 #define CLK_DOUT_MFCMSCL_JPEG          75
-#define TOP_NR_CLK                     76
+#define CLK_MOUT_G3D_SWITCH            76
+#define CLK_GOUT_G3D_SWITCH            77
+#define CLK_DOUT_G3D_SWITCH            78
+#define TOP_NR_CLK                     79
 
 /* CMU_APM */
 #define CLK_RCO_I3C_PMIC               1
 #define CLK_GOUT_SYSREG_CMGP_PCLK      15
 #define CMGP_NR_CLK                    16
 
+/* CMU_G3D */
+#define CLK_FOUT_G3D_PLL               1
+#define CLK_MOUT_G3D_PLL               2
+#define CLK_MOUT_G3D_SWITCH_USER       3
+#define CLK_MOUT_G3D_BUSD              4
+#define CLK_DOUT_G3D_BUSP              5
+#define CLK_GOUT_G3D_CMU_G3D_PCLK      6
+#define CLK_GOUT_G3D_GPU_CLK           7
+#define CLK_GOUT_G3D_TZPC_PCLK         8
+#define CLK_GOUT_G3D_GRAY2BIN_CLK      9
+#define CLK_GOUT_G3D_BUSD_CLK          10
+#define CLK_GOUT_G3D_BUSP_CLK          11
+#define CLK_GOUT_G3D_SYSREG_PCLK       12
+#define G3D_NR_CLK                     13
+
 /* CMU_HSI */
 #define CLK_MOUT_HSI_BUS_USER          1
 #define CLK_MOUT_HSI_MMC_CARD_USER     2