clk: renesas: r8a779g0: Add CMT clocks

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221104151135.4706-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 7f0b4f75ff4d812c6200da23037bf6b8897c8994..1da48c81d3ddf3dfd129a42773cd3721003c3b93 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -193,6 +193,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("tmu4",         717,    R8A779G0_CLK_SASYNCPERD2),
        DEF_MOD("tpu0",         718,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("wdt1:wdt0",    907,    R8A779G0_CLK_R),
+       DEF_MOD("cmt0",         910,    R8A779G0_CLK_R),
+       DEF_MOD("cmt1",         911,    R8A779G0_CLK_R),
+       DEF_MOD("cmt2",         912,    R8A779G0_CLK_R),
+       DEF_MOD("cmt3",         913,    R8A779G0_CLK_R),
        DEF_MOD("pfc0",         915,    R8A779G0_CLK_CL16M),
        DEF_MOD("pfc1",         916,    R8A779G0_CLK_CL16M),
        DEF_MOD("pfc2",         917,    R8A779G0_CLK_CL16M),